Zobrazeno 1 - 10
of 76
pro vyhledávání: '"T. Webers"'
Autor:
M. Peeters, S. Sinha, X. Sun, C. Desset, G. Gramegna, J. Slabbekoorn, P. Bex, N. Pinho, T. Webers, D. Velenis, A. Miller, N. Collaert, G. Van der Plas, E. Beyne, M. Huynen, R. Broucke
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a83b41766355426f0784d538a739e55
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830480
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830480
Autor:
Philippe Leray, N. Jourdan, O. Varela Pedreira, E. Dentoni-Litta, Thomas Witters, Werner Gillijns, Nancy Heylen, L. Ramakers, E. Grieten, Zaid El-Mekki, Gayle Murdoch, V. Vega-Gonzalez, Anne-Laure Charley, Ivan Ciofi, Zsolt Tokei, H. Vats, S. V. Gompel, M. H. van der Veen, L. Halipre, J. Swerts, A. Haider, Bilal Chehab, S. Park, N. Bazzazian, Quoc Toan Le, B. De Wachter, T. Peissker, Harinarayanan Puliyalil, Naoto Horiguchi, Miroslav Cupak, J. Versluijs, G. T. Martinez, Y. Kimura, R. Kim, J. Geypen, J. Uk-Lee, N. Nagesh, D. Montero, L. Rynders, M. Ercken, D. Batuk, K. Croes, Patrick Verdonck, Manoj Jaysankar, Y. Drissi, T. Webers
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::775097fabe7d875876eeac9844668bb1
https://doi.org/10.1109/iitc51362.2021.9537535
https://doi.org/10.1109/iitc51362.2021.9537535
Autor:
Ehsan Shafahian, Carine Gerets, Eric Beyne, Masataka Maehara, Vladimir Cherman, G. Jamieson, Pieter Bex, Jaber Derakhshandeh, Inge De Preter, Julien Bertheau, Andy Miller, Fumihiro Inoue, T. Webers, Melina Lofrano, Tom Cochet, Lin Hou, Giovanni Capuz, Geert Van der Plas, Gerald Beyer, Douglas Charles La Tulipe
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
In this paper full integration flow for a low temperature (150°C) and high throughput die to wafer bonding method is introduced for microbumps pitches down to $10 \mu \mathrm{m}$ . The impact of Co plating chemistry, Sn thickness, annealing temperat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cfeeb4cc427d4dab249085f66d02da8
https://doi.org/10.1109/ectc32696.2021.00183
https://doi.org/10.1109/ectc32696.2021.00183
Autor:
Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, T. Webers
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d5b5a73112c7be6f5016d4aa4c44eb7
https://doi.org/10.1109/iedm13553.2020.9372096
https://doi.org/10.1109/iedm13553.2020.9372096
Autor:
Joeri De Vos, Herman Oprins, Eric Beyne, T. Webers, Vladimir Cherman, Geert Van der Plas, Soon-Wook Kim
Publikováno v:
2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).
3D wafer-to-wafer bonding is a promising fabrication method to create 3D systems with a very high interconnect density. The thermal resistance of the 3D bonding interface can represent a significant contribution of the overall thermal resistance in t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b05242f652985a4b63a3147b2bd58953
https://doi.org/10.1109/itherm45881.2020.9190392
https://doi.org/10.1109/itherm45881.2020.9190392
Autor:
Ehsan Shafahian, Gerald Beyer, Inge De Preter, Carine Gerets, Eric Beyne, Fumihiro Inoue, Jaber Derakhshandeh, Giovanni Capuz, Julien Bertheau, Andy Miller, Fabrice Duval, Alain Phommahaxay, Pieter Bex, T. Webers, Geert Van der Plas, Stefaan Van Huylenbroeck, Lin Hou, Vladimir Cherman
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
In this paper, spacer bumps concept is introduced to increase the process window for TCB, lower the sensitivity of electrical yield to bump height variation, maintain the gap between two dies and to prevent too much solder deformation for a test vehi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65abb2efc3d3b50eedb9705562af5988
https://doi.org/10.1109/ectc32862.2020.00102
https://doi.org/10.1109/ectc32862.2020.00102
Autor:
Geert Van der Plas, Giacomo Talmelli, Tom Sterken, Christoph Adelmann, Xiao Sun, Dimitrios Velenis, John Slabbekoorn, Andy Miller, T. Webers, Pieter Bex, Eric Beyne, Inge De Preter, Fabrice Duval
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
This paper demonstrates that fan-out wafer-level packaging (FOWLP) can enable high-Q integrated passive devices (IPDs) on low-loss mold compound materials. Moreover, we show that thick ferrite cores can be embedded into FOWLP, further enhancing the R
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6cc04cee0629b9738567720b025bff9
https://doi.org/10.1109/ectc32862.2020.00216
https://doi.org/10.1109/ectc32862.2020.00216
Autor:
V. Vega-Gonzalez, J. Bekaert, E. Kesters, Q. T. Le, C. Lorant, O. Varela P., L. Teugels, N. Heylen, Z. El-Mekki, M. van der Veen, T. Webers, C. J. Wilson, H. Vats, L. Rynders, M. Cupak, J. Uk-Lee, Y. Drissi, L. Halipre, A.-L. Charley, P. Verdonck, T. Witters, S. V. Gompel, B. Briggs, Y. Kimura, N. Jourdan, I. Ciofi, A. Gupta, A. Contino, G. Boccardi, S. Lariviere, L. Dupas, B. De-Wachter, E. Vancoille, S. Decoster, F. Lazzarino, M Ercken, P. Debacker, R. Kim, D. Trivkovic, K. Croes, P. Leray, L. Dillemans, Y.-F. Chen, Z. Tokei, J. Versluijs, A. Lesniewska, S. Paolillo, R. Baert, H. Puliyalil
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7eecb12b8a386042eac7e3255fe54876
https://doi.org/10.1109/iedm19573.2019.8993538
https://doi.org/10.1109/iedm19573.2019.8993538
Autor:
John Slabbekoorn, Jaber Derakhshandeh, Melina Lofrano, Julien Bertheau, Andy Miller, Lin Hou, Fumihiro Inoue, M. Honore, Fabrice Duval, Vladimir Cherman, Kenneth June Rebibis, F. Beirnaert, Gerald Beyer, G. Jamieson, Giovanni Capuz, Samuel Suhard, C. Heyvaert, Nancy Heylen, I. De Preter, Carine Gerets, Eric Beyne, T. Webers, Alain Phommahaxay, G. Van der Plas, Pieter Bex, Tom Cochet
Publikováno v:
2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC).
In this paper a novel solder-based die-to-die or wafer-to-wafer interconnect approach is introduced. This technique allows for microbump interconnects with different diameters on a single die and allows for pitch scaling down to 5μm A metal damascen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::023c4836b336797eba252150c2054bc7
https://doi.org/10.23919/empc44848.2019.8951856
https://doi.org/10.23919/empc44848.2019.8951856
Autor:
Eric Beyne, Geert Van der Plas, Vladimir Cherman, Soon-Wook Kim, Herman Oprins, T. Webers, Lan Peng, Abdellah Salahouelhadj
Publikováno v:
2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).
In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of Line (BEOL) for the experimental thermal characterization of the inter-die thermal resistance of wafer-pairs fabricated b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd60d5f5eedc95bbeab42cd5362c77a5
https://doi.org/10.1109/itherm.2016.7517703
https://doi.org/10.1109/itherm.2016.7517703