Zobrazeno 1 - 10
of 24
pro vyhledávání: '"T. Waayers"'
Publikováno v:
Journal of Electronic Testing. 19:417-424
This paper describes an architecture for controlling multiple IEEE 1149.1 compliant TAP controllers on a single digital system chip. The key feature of this architecture is the compatibility with the IEEE 1149.1 standard, and existing debugger softwa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1f0310e0f678c27e07e14c9cb075891
https://doi.org/10.1023/a:1024691909923
https://doi.org/10.1023/a:1024691909923
Publikováno v:
Journal of Electronic Testing. 18:129-143
This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide acce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0a412cede50af15c7e0f6dda930fd2c
https://doi.org/10.1023/a:1014989408897
https://doi.org/10.1023/a:1014989408897
Publikováno v:
ITC
This paper presents a new modular SOC test architecture that uses an improved single TAM daisy-chain for scan test access to embedded modules. The architecture by definition guarantees that the total SOC test time is close to the lower bound. To make
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3b3420c7dcb8dcb1a2d48194a45ab75
https://doi.org/10.1109/test.2005.1584022
https://doi.org/10.1109/test.2005.1584022
Autor:
G. Seuren, T. Waayers
Publikováno v:
ITC
This work presents an extension to a digital core-based test architecture to support testing of mixed-signal cores in a system-on-chip. It also presents a new mixed-signal test development flow that comprises a test library based approach to ease mix
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df7097b9806aaab9b1b719509b78f269
https://doi.org/10.1109/test.2004.1386962
https://doi.org/10.1109/test.2004.1386962
Publikováno v:
Asian Test Symposium
Modern semiconductor process technologies enable the manufacturing of a complete system on one single die, the so-called system-on-chip or SOC. Building those chips in a timely and cost-effective manner is amongst others realized by embedding third-p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d21623abf21c366a01c0bce3d473c73
https://doi.org/10.1109/ats.2005.67
https://doi.org/10.1109/ats.2005.67
Autor:
E.J. Marinissen, T. Waayers
Publikováno v:
CICC
Large single-die system chips are designed in a modular fashion, including and reusing pre-designed and pre-verified design blocks. Modular testing is required for embedded non-logic modules and black-boxed IP cores. Also, modular testing is attracti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86c332651fd4abad5c38c0ebcb9a2bbe
https://doi.org/10.1109/cicc.2004.1358916
https://doi.org/10.1109/cicc.2004.1358916
Publikováno v:
ITC
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to check signals. Access to these pins is becoming more difficult due to pack
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a163c7a54a9d9bed06527a2276d64ef4
https://doi.org/10.1109/test.2003.1270910
https://doi.org/10.1109/test.2003.1270910
Publikováno v:
ITC
To enable the efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be re-used in one, well-defined debug architectures at chip-level. This paper describes a chip-level architecture for control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::201a9b2e405b5d701cfd391d2bfa8a33
https://doi.org/10.1109/test.2002.1041745
https://doi.org/10.1109/test.2002.1041745
Publikováno v:
MTDT
We describe the design and implementation of an IEEE P1500 compliant programmable BIST for embedded memories. The proposed design can be embedded in other cores or systems with minimum test generation or test application overhead. The programmability
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::386fd771ce407d3d2ce4d615591626bc
https://doi.org/10.1109/mtdt.2001.945224
https://doi.org/10.1109/mtdt.2001.945224
Publikováno v:
ITC
This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide acce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50b038b7cc124c1cc7e28b61b0fb75e3
https://doi.org/10.1109/test.2001.966695
https://doi.org/10.1109/test.2001.966695