Zobrazeno 1 - 10
of 90
pro vyhledávání: '"T. Vandeweyer"'
Autor:
Aaron Thean, Eddy Simoen, T. Vandeweyer, S. Locorotondo, Nadine Collaert, Anne S. Verhulst, Andriy Hikavyy, Roger Loo, Katia Devriendt, Anne Vandooren, George Bryce, Rita Rooyackers, Marc Demand, Cedric Huyghebaert, Amey Mahadev Walke
Publikováno v:
IEEE Transactions on Electron Devices. 61:4032-4039
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a590d17fe287e08674d95f091e5eaef7
https://doi.org/10.1109/ted.2014.2365142
https://doi.org/10.1109/ted.2014.2365142
Autor:
Andrew Cross, M. Stoerring, T. Vandeweyer, S. Hiebert, Shifang Li, J. De Vos, Andy Miller, G. Bast, Anne Jourdain, M. Liebens, Eric Beyne
Publikováno v:
2017 28th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Device packaging techniques continue to evolve. Modern packages connect components directly using different 3-D interconnect technologies. As the 3-D interconnect density is increasing exponentially, pitches need to reduce. Current interconnect techn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4fe01ca545db4bd35b3f6278007edae3
https://doi.org/10.1109/asmc.2017.7969255
https://doi.org/10.1109/asmc.2017.7969255
Autor:
John Slabbekoorn, Bert Tobback, Andy Miller, Warren W. Flack, P. Czarnecki, Gareth Kenyon, Michele Stucchi, Stefaan Van Huylenbroeck, T. Vandeweyer, Robert Hsieh
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14edb796fc57e2f9bd0d4e0c0bf428b2
https://doi.org/10.1109/eptc.2016.7861543
https://doi.org/10.1109/eptc.2016.7861543
Autor:
Johan Wouters, Stefan Kubicek, D. L. Diehl, Malgorzata Jurczak, Katia Devriendt, Rita Rooyackers, Virginie Gravey, T. Y. Hoffmann, Naoto Horiguchi, Denis Shamiryan, T. Vandeweyer, A. Cockburn, Erik Sleeckx, Augusto Redolfi, M. Togo, Tinne Delande, Min-Soo Kim
Publikováno v:
Solid-State Electronics. 71:106-112
This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69991887c91fcfb3f4b8f6711f09844d
https://doi.org/10.1016/j.sse.2011.10.029
https://doi.org/10.1016/j.sse.2011.10.029
Autor:
Stephan Brus, S. Verhaegen, Efrain Altamirano-Sanchez, Anabela Veloso, C. Delvaux, M. Ercken, Christina Baerts, Marc Demand, T. Vandeweyer, J. De Backer, S. Locorotondo, Naoto Horiguchi
Publikováno v:
Microelectronic Engineering. 87:993-996
FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22nm node 6T-SRAM cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9483254ad9233fa51abceefc7885662d
https://doi.org/10.1016/j.mee.2009.11.119
https://doi.org/10.1016/j.mee.2009.11.119
Autor:
Denis Shamiryan, Rita Rooyackers, T. Vandeweyer, J. Van Puymbroeck, Werner Boullart, Malgorzata Jurczak, Nadine Collaert, Bart Degroote, Eddy Kunnen, J. Wouters, Abhisek Dixit
Publikováno v:
Microelectronic Engineering. 84:609-618
We present a method to obtain Si-fins with a critical dimension (CD) below 20nm, separated by a minimum distance of 25nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c19da2fb9c29fce0a4a5eae4b0b07c96
https://doi.org/10.1016/j.mee.2006.12.003
https://doi.org/10.1016/j.mee.2006.12.003
Autor:
Ryutaro Yasuhara, Akifumi Kawahara, Satoru Ito, E. Vecchio, Z. Wei, S. Fujii, Yoshio Kawashima, Kazuhiko Shimakawa, Ken Kawai, Yuichiro Ikeda, Thomas Witters, S. Muraoka, Werner Boullart, Malgorzata Jurczak, T. Vandeweyer, Takumi Mikawa, D. Crotti, Atsushi Himeno, Shinichi Yoneda, Yukio Hayakawa
Publikováno v:
VLSIC
For 28-nm embedded application, we have proposed a TaO x -based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies and cell structures: low-damage etching, cell
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4407ca7cee154d5c2496eae31d0fc7a8
https://doi.org/10.1109/vlsit.2015.7223684
https://doi.org/10.1109/vlsit.2015.7223684
Autor:
Alexis Farcy, D. Bouchu, F. Gaillard, Romano Hoofman, L.G. Gosset, Joaquim Torres, Pascal Bancken, V. Nguyen Hoang, Greja Johanna Adriana Maria Verheijden, J. Michelon, T. Vandeweyer, Ph. Lyan, Roel Daamen, J. de Pontcharra, Vincent Arnal
Publikováno v:
Microelectronic Engineering. 82:321-332
The integration of air gaps for advanced Cu interconnects is mandatory to achieve the performances required for high performance integrated circuits (ICs). The interest of their introduction as a function of the chosen architecture, i.e. hybrid (i.e.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8034fc4e79c100236edbe24d975b291f
https://doi.org/10.1016/j.mee.2005.07.014
https://doi.org/10.1016/j.mee.2005.07.014
Publikováno v:
Microelectronic Engineering. 88:2171-2173
Exploration on device scaling in the semiconductor industry is mainly looking into the critical layers, like active, gate, contact and metal1. Double patterning and EUV lithography have already been introduced to enable this scaling for future needs.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fae861165c10c34907af888f2ad39e23
https://doi.org/10.1016/j.mee.2010.12.088
https://doi.org/10.1016/j.mee.2010.12.088
Autor:
Tinne Delande, Herbert Struyf, Patrick Ong, T. Vandeweyer, Diana Tsvetanova, Soon Aik Chew, Naoto Horiguchi, Katia Devriendt
Publikováno v:
Proceedings of International Conference on Planarization/CMP Technology 2014.
The Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) process has an essential role in the STI module for the fabrication of the Complementary Metal Oxide Semiconductor (CMOS) transistors. Since the 0.13 μηι technology node a dire
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f00bb8149c1cc5999e5b89c18d8c3d5d
https://doi.org/10.1109/icpt.2014.7017279
https://doi.org/10.1109/icpt.2014.7017279