Zobrazeno 1 - 10
of 14
pro vyhledávání: '"T. V. S. Ram"'
Autor:
Richa Sharma Kesarkar, Deepak Attri, Mohd Azhar R Saiyed, T V S Ram, K S Parikh, Thejesh N Bandi
Publikováno v:
Journal of Thermal Analysis and Calorimetry. 147:10049-10056
Publikováno v:
The Review of scientific instruments. 92(12)
In many low-noise applications, extracting information from the extremely noisy signal is required. This task can be accomplished by a lock-in amplifier if the frequency of the signal is known before detection. Error signal output from the physics pa
Publikováno v:
2021 8th International Conference on Signal Processing and Integrated Networks (SPIN).
Onboard digital processors are the emerging technological developments in the arena of satellite communication for its on-board flexibility, configurability and programmability. SSPAs (Solid State Power amplifiers) are common components in the RF cha
Autor:
Deepak Attri, Richa U. Sharma, A. I. Patel, Azhar R. Saiyed, Sandip Somani, Deepak Mishra, Sarathi Mandal, Jaydeep Kaintura, Bikash Ghosal, T. V. S. Ram, Priyanka Priya, K. S. Parikh, Ashish Soni, Pratik Jain, Niranjan Reddy, Keya Shukla, Thejesh N. Bandi
Publikováno v:
2019 URSI Asia-Pacific Radio Science Conference (AP-RASC).
Navigation is an indispensable part of everyday human life. In recent times, satellite based navigation system has proven to be indispensable in various navigation and scientific applications [1]. The backbone of satellite based navigation systems is
Publikováno v:
2019 6th International Conference on Signal Processing and Integrated Networks (SPIN).
This paper gives the design and implementation of Xilinx FPGA based Forward Error Correction (FEC) encoder for DVB S2 system which includes BCH code followed by LDPC code and finally bit mapped to constellation for QPSK modulation. DVB-S2 FEC: ( $\ma
Publikováno v:
2016 IEEE Annual India Conference (INDICON).
This paper presents the design and implementation of an effective Single Event Upset (SEU) mitigation technique for radtolerant Xilinx virtex-4xqr4vsx55FPGA used in Digital Bandwidth Efficient Filter (DBEF) subsystem for a Geostationary mission. The
Publikováno v:
ICACCI
An open standard compatible onboard processing system is under development, which provides mesh connectivity between different user terminals. The system is designed to be compatible to Digital Video Broadcasting — Return Channel via Satellite (DVB
Publikováno v:
2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN).
This paper describes the design and in-house development of FPGA based Digital Beam Forming Hardware for 16 elements configuration. Key function of the System involves electronic steering of beam in desired direction to provide anti-jamming feature i
Publikováno v:
2015 Annual IEEE India Conference (INDICON).
The communication links at high speed requires bit synchronizer for countering bit phase misalignment at the receive end. This paper describes the design of IC based digital bit synchronizer for high speed optical communication links. It supports dat
Publikováno v:
VDAT
There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability