Zobrazeno 1 - 10
of 114
pro vyhledávání: '"T. Uchikoba"'
Autor:
N. Kuroda, Miho Miura, Hirohito Kikukawa, Hiroyuki Yamauchi, Y. Agata, K. Egashira, T. Uchikoba, T. Kawasaki, K. Takahashi, M. Shirahama, S. Hashimoto, S. Honda, H. Sadakata, W. Abe, R. Nishihara
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:1200-1207
This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro
Autor:
M. Ishikawa, A. Shibayama, Shigeki Tomishima, M. Senoh, H. Tanizaki, Hideto Hidaka, M. Maruta, T. Inokuchi, T. Kawasaki, Tsukasa Ooishi, W. Abe, K. Takahashi, S. Sakamoto, Hirohito Kikukawa, H. Kato, Y. Fukushima, Takaharu Tsuji, M. Nirro, T. Uchikoba
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:932-940
This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm/sup 2/ and cell efficiency of 51.3% for the
Autor:
W. Abe, H. Tanizaki, Hirohito Kikukawa, T. Kawasaki, Takaharu Tsuji, H. Kato, Tsukasa Ooishi, M. Ishikawa, K. Takahashi, M. Maruta, Hideto Hidaka, S. Sakamoto, Y. Fukushima, T. Inokuchi, T. Uchikoba, Shigeki Tomishima, A. Shibayama, M. Niiro, M. Senoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1728-1737
This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even
Autor:
S. Hashimoto, R. Nishihara, N. Kuroda, M. Shirahama, I. Kawasaki, K. Takahashi, S. Honda, Hiroyuki Yamauchi, T. Uchikoba, M. Miura, H. Sadakata, Y. Agata, W. Abe, K. Egashira, H. Kikukawa
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
We present a 400MHz random-cycle dual-port interleaved 1.5V DRAM macro with fully sense-signal-loss compensating technologies based on noise-element breakdowns, a striped trench capacitor cell and write-before-sensing by a decoded write-bus circuit t
Autor:
Takaharu Tsuji, H. Tanizaki, M. Ishikawa, Hideto Hidaka, M. Niiro, K. Takahashi, Akinori Shibayama, M. Senoh, T. Uchikoba, Shigeki Tomishima, Hirohito Kikukawa, T. Inokuchi, Y. Fukushima, H. Kato, S. Sakamoto, M. Maruta, T. Ooishi, W. Abe, T. Kawasaki
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
Previous embedded DRAMs (eDRAMs) have the dual ports on the sense amplifier and wide I/O buses on memory arrays for high data rate in graphic controller chips. This causes decreased cell efficiency and increased power consumption in burst operation c
Publikováno v:
Journal of Nippon Medical School = Nippon Ika Daigaku zasshi. 68(3)
Publikováno v:
Hinyokika kiyo. Acta urologica Japonica. 46(7)
An 88-year-old patient with a poorly differentiated adenocarcinoma of the prostate gland was found to have all cardinal findings of syndrome of inappropriate antidiuretic hormone secretion (SIADH). Elevated levels of antidiuretic hormone were found i
Publikováno v:
Biotechnology and applied biochemistry. 22(2)
Cucumisin (EC 3.4.21.25), a serine endopeptidase, was isolated by a simple purification procedure from the prince melon (Cucumis melo ssp. melo, cv. 'Prince Melon'). The enzyme is stable over a wide pH range (4-11) and to heat, 80% of its initial act
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Akademický článek
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