Zobrazeno 1 - 10
of 21
pro vyhledávání: '"T. Sukemura"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1229-1236
A 54-b*54-b parallel multiplier was implemented in 0.88- mu m CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::449712d1f27b56986558025689878f61
https://doi.org/10.1109/4.149426
https://doi.org/10.1109/4.149426
Publikováno v:
1991 Symposium on VLSI Circuits.
In this paper, we describe a 112-bit transmission gate adder utilizing a new bypass circuit control scheme to improve performance. The estimated propagation delay time is 8.5 ns and the number of transistors is 6,941, both of which are smaller than t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3de504b16b338baf9849bc051370bbb3
https://doi.org/10.1109/vlsic.1991.760100
https://doi.org/10.1109/vlsic.1991.760100
Publikováno v:
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
Reports on a single-chip supercomputer vector processing unit (VPU) which achieves peak performance of 149 MFLOPS for double-precision operation and 289 MFLOPS for single-precision operation with 560 MB/s bus bandwidth at 70 MHz. The VPU chip, fabric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ae641b3289ebc2b138fb149017c8595
https://doi.org/10.1109/isscc.1992.200437
https://doi.org/10.1109/isscc.1992.200437
Autor:
Hiroshi Okano, T. Satoh, Hiroshi Takahashi, M. Saito, H. Utsumi, T. Katayama, T. Saruwatari, Y. Takebe, M. Kimura, M. Tsuji, Hideo Miyake, Atsuhiro Suga, T. Sukemura, Yoshio Hirose
Publikováno v:
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).
A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::201f9d2df428e9f523c65bac445dc825
https://doi.org/10.1109/apasic.2000.896984
https://doi.org/10.1109/apasic.2000.896984
Autor:
K. Wada, T. Sukemura, Y. Hirose, K. Abe, T. Shiota, M. Kimura, T. Satoh, S. Wakayama, M. Saito, T. Ozawa, T. Okano, Hideo Miyake, A. Sakurai, Yasuki Nakamura, K. Kuwano, Y. Takebe, I. Azegami, Atsuhiro Suga, Hiromasa Takahashi, T. Katayama
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
Performance requirements are soaring for embedded processors, whose demand in multimedia processing is rising now more than ever. Some DSP and media processors satisfy this by means of VLIW architecture. However, for embedded processors, less code, l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::409a0dcd20d753df3ff9cdcdd5f84872
https://doi.org/10.1109/isscc.2000.839767
https://doi.org/10.1109/isscc.2000.839767
Autor:
H. Okano, A. Suga, T. Shiota, Y. Takebe, Y. Nakamura, N. Higaki, H. Kimura, H. Miyake, T. Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, M. Sasaki, N. Ando, T. Yamana, I. Fukushi, S. Tago, F. Hayakawa, T. Kamigata, S. Imai, A. Satoh, Y. Hatta, N. Nishimura, Y. Asada, T. Sukemura, S. Ando, H. Takahashi
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c641dc2b48048f8b8ed16c97c9f7964c
https://doi.org/10.1109/isscc.2002.993088
https://doi.org/10.1109/isscc.2002.993088
Autor:
H. Okano, A. Suga, T. Shiota, Y. Takebe, Y. Nakamura, N. Higaki, H. Kimura, H. Miyake, Tomio Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, M. Sasaki, N. Ando, T. Yamana, I. Fukushi, S. Tago, F. Hayakawa, T. Kamigata, S. Imai, A. Satoh, Y. Hatta, N. Nishimura, Y. Asada, Taizo Satoh, T. Sukemura, S. Ando, H. Takahashi
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3301db103654e031c8cd0e79fda996e7
https://doi.org/10.1109/isscc.2002.992265
https://doi.org/10.1109/isscc.2002.992265
Publikováno v:
Journal of Physics: Conference Series. 500:182022
High-pressure Raman scattering experiments were performed for type-I Sn based clathrates, Ba8Ga16Sn30, at room temperature up to 6.9 GPa. We observed irreversible amorphization at 6 GPa. The rattling vibrations of the guest atoms in the cages were in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cbaffb590846fbd3b74fba5b37d0d7b
https://doi.org/10.1088/1742-6596/500/18/182022
https://doi.org/10.1088/1742-6596/500/18/182022
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:657-659
The authors discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2527f4bbfae66032c96ed7c91360073f
https://doi.org/10.1109/4.126557
https://doi.org/10.1109/4.126557
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.