Zobrazeno 1 - 10
of 32
pro vyhledávání: '"T. Rinderknecht"'
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Autor:
P. Reuter, B. Swanson, Xijiiang Lin, Janusz Rajski, T. Rinderknecht, Nagesh Tamarapalli, Ron Press
Publikováno v:
IEEE Design & Test of Computers. 20:17-25
The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a543e300762b328178858d6d86a5ce5
https://doi.org/10.1109/mdt.2003.1232252
https://doi.org/10.1109/mdt.2003.1232252
Publikováno v:
Asian Test Symposium
In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a413f03556ba07a53dd817116f8c9952
https://doi.org/10.1109/ats.2013.45
https://doi.org/10.1109/ats.2013.45
Publikováno v:
DFT
As digital circuits grow in gate count so does the data volume required for manufacturing test. To address this problem several test compression techniques have been developed. This paper presents a novel and scalable technique for inserting observat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::205393053001c2a93862c00573b04d03
https://doi.org/10.1109/dft.2008.39
https://doi.org/10.1109/dft.2008.39
Publikováno v:
16th Asian Test Symposium (ATS 2007).
This paper presents a programmable approach for performing scan-based logic built-in self test. This approach combines the techniques of reseeding and weighted random patterns testing. Reseeding is used to encode the bias cube and weighted patterns a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63abbd830fff1c125803b20e5d9aa886
https://doi.org/10.1109/ats.2007.45
https://doi.org/10.1109/ats.2007.45
Publikováno v:
ICCD
In this paper, a novel logic BIST (built-in self test) scheme with complementary weights is proposed. The BIST implementation combines random patterns with complementary-weight weighted patterns. A heuristic algorithm based on deterministic test set
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::133141520e76e4a5af68f0ff12fc02bd
https://doi.org/10.1109/iccd.2005.63
https://doi.org/10.1109/iccd.2005.63
Publikováno v:
ITC
This work presents a novel BIST (built-in self test) scheme with scan chain segmentation. In the scheme, a combination of pseudo random patterns and single-weight patterns have been applied to CUT (circuit under test). Scan chain is partitioned into
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06b5bae4a0b8ac18b09d2901d8c87cc0
https://doi.org/10.1109/test.2004.1386937
https://doi.org/10.1109/test.2004.1386937
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
VLSI Design
This paper presents state-of -the-art embedded test technology, practices, and automation tools for high-quality low cost manufacturing test. Embedded test structures are focused and pseudo random versus deterministic forms are compared. This paper c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4b1712fa44d23e7b3eee849c97117abe
https://doi.org/10.1109/icvd.2004.1260896
https://doi.org/10.1109/icvd.2004.1260896