Zobrazeno 1 - 10
of 30
pro vyhledávání: '"T. Ohnakado"'
Publikováno v:
IEEE Transactions on Electron Devices. 48:863-867
A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::646b64f52c32928c69b01c9da6d5ffff
https://doi.org/10.1109/16.918232
https://doi.org/10.1109/16.918232
Autor:
T. Ohnakado, S. Satoh
Publikováno v:
IEEE Transactions on Electron Devices. 47:1209-1213
This paper describes a novel self-limiting high-speed program scheme of the p-channel DINOR (D_I_vided bit line N_O_R_) flash memory utilizing n-channel select transistors. This scheme makes it possible to maintain the high programming throughput of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::703c690fcdf254a45d10ca0398816999
https://doi.org/10.1109/16.842963
https://doi.org/10.1109/16.842963
Autor:
K. Hayashi, N. Ajika, S. Satoh, T. Ohnakado, H. Onoda, K. Sugahara, Osamu Sakamoto, H. Takada, N. Nishioka
Publikováno v:
IEEE Transactions on Electron Devices. 46:1866-1871
The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-/spl mu/m-rule CMOS proc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::056767be8e1917b935b9a4f6a5061fd3
https://doi.org/10.1109/16.784186
https://doi.org/10.1109/16.784186
Autor:
Yasuhiro Kagawa, Akihiko Furukawa, S. Maegawa, T. Ipposhi, Satoshi Yamakawa, Yuuichi Hirano, Kazuyasu Nishikawa, T. Ikeda, M. Takeda, T. Ohnakado, H. Arima, Kenji Shintani
Publikováno v:
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.
This paper describes the experimental characteristics of RF components with layout and structural optimization, fabricated in 0.10-/spl mu/m 1.2-V SOI-CMOS technology with partial trench isolation (PTI). ESD protection-grounded gate SOI-NMOSFETs achi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ab75588ea17f30f95c2f68fe82f6e75
https://doi.org/10.1109/rfic.2006.1651094
https://doi.org/10.1109/rfic.2006.1651094
Publikováno v:
International Electron Devices Meeting. Technical Digest.
This paper describes a novel self-limiting program scheme applying N-channel select transistors in the P-channel DINOR flash memory, which makes it possible to maintain the high programming throughput even for future lower-voltage flash memories. Usi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0216f22a51241b3a440734abe483701b
https://doi.org/10.1109/iedm.1996.553149
https://doi.org/10.1109/iedm.1996.553149
Autor:
Hiroshi Onoda, Hirokazu Miyoshi, N. Tsuji, H. Takada, Osamu Sakamoto, N. Yamasaki, M. Hatanaka, K. Hayashi, N. Ajika, T. Katayama, Kiyohiko Sakakibara, T. Ohnakado
Publikováno v:
1996 Symposium on VLSI Technology. Digest of Technical Papers.
A high programming throughput p-channel DINOR flash memory with the BBHE injection programming method has been developed using 0.35 /spl mu/m CMOS process. This programming method realizes a high programming throughput of 8 nsec/Byte by utilizing 512
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79660ef2d175f82501f408885cca239c
https://doi.org/10.1109/vlsit.1996.507858
https://doi.org/10.1109/vlsit.1996.507858
1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells
Autor:
Hideki Hayashi, H. Takada, N. Ajika, K. Kobayashi, Shinichi Satoh, Hirokazu Miyoshi, T. Ohnakado, K. Sugahara
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the adva
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6306fbc7da4bdceb6ecba4f76c82daba
https://doi.org/10.1109/vlsit.1998.689180
https://doi.org/10.1109/vlsit.1998.689180
Autor:
K. Mitsunaga, Hirokazu Miyoshi, M. Nunoshita, N. Tsuji, M. Hatanaka, Hiroshi Onoda, Kiyohiko Sakakibara, T. Ohnakado, Natsuo Ajika
Publikováno v:
Proceedings of International Electron Devices Meeting.
A novel electron injection scheme for flash memory is proposed, where band-to-band tunneling induced hot electrons (BBHE) are employed in a P-channel cell. This proposed method ensures the realization of high program efficiency, high scalability and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7416f4e78b2abdefa8cb1ba25de4bf60
https://doi.org/10.1109/iedm.1995.499196
https://doi.org/10.1109/iedm.1995.499196
Autor:
G. Campardo, R. Micheloni, S. Commodaro, E. Yero, M. Zammabio, S. Mognoni, A. Sacco, M. Picca, A. Manstleita, M. Scotti, I. Motta, C. Golla, A. Pierin, A. Ohba, T. Fulatsuya, R. Makabe, S. Kawai, Y. Kai, S. Shimizu, T. Ohnakado, I. Sugihara, R. Bez, A. Grossi, A. Modelli, P.O. Khouri, G. Torelli
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
The ever increasing demand for denser flash memories leads to the multilevel (ML) storage approach, where any memory cell is programmed to one of m=2/sup n/ predetermined states and can hence store n bits. This 64 Mb 4-level cell (2b/cell) flash memo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbdd72be53fcbc01649137483f723115
https://doi.org/10.1109/isscc.2000.839782
https://doi.org/10.1109/isscc.2000.839782
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