Zobrazeno 1 - 10
of 13
pro vyhledávání: '"T. Mota Frutuoso"'
Publikováno v:
IEEE Transactions on Electron Devices. 70:845-849
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c22e0d8232fb9d704272b8c766400a15
https://doi.org/10.1109/ted.2022.3215097
https://doi.org/10.1109/ted.2022.3215097
Autor:
C. Doyen, V. Yon, X. Garros, L. Basset, T. Mota Frutuoso, C. Dagon, C. Diouf, X. Federspiel, V. Millon, F. Monsieur, C. Pribat, D. Roy
Publikováno v:
2023 IEEE International Reliability Physics Symposium (IRPS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d32e8a84fd239457ce9b37d14af3dbf
https://doi.org/10.1109/irps48203.2023.10117681
https://doi.org/10.1109/irps48203.2023.10117681
Autor:
T. Mota Frutuoso, X. Garros, P. Batude, L. Brunet, J. Lacord, B. Sklenard, V. Lapras, C. Fenouillet-Beranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, E. Catapano, M. Casse, J. Lugo-Alvarez, P. Ferrari, F. Gaillard
Publikováno v:
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022)
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Jun 2022, Honolulu (HI), United States. ⟨10.1109/VLSITechnologyandCir46769.2022.9830504⟩
IEEELink
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Jun 2022, Honolulu (HI), United States. ⟨10.1109/VLSITechnologyandCir46769.2022.9830504⟩
IEEELink
International audience; We present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500°C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9eef2750dbb3aeee813a581581b63000
https://hal.science/hal-04069091
https://hal.science/hal-04069091
Autor:
P. Batude, O. Billoint, S. Thuries, P. Malinge, C. Fenouillet-Beranger, A. Peizerat, G. Sicard, P. Vivet, S. Reboh, C. Cavalcante, L. Brunet, M. Ribotta, L. Brevard, X. Garros, T. Mota Frutuoso, B. Sklenard, J. Lacord, J. Kanyandekwe, S. Kerdiles, P. Sideris, C. Theodorou, V. Lapras, M. Mouhdach, G. Gaudin, G. Besnard, I. Radu, F. Ponthenier, A. Farcy, E. Jesse, F. Guyader, T. Matheret, P. Brunet, F. Milesi, L. Le Van-Jodin, A. Sarrazin, B. Perrin, C. Moulin, S. Maitrejean, M. Alepidis, I. Ionica, S. Cristoloveanu, F. Gaillard, M. Vinet, F. Andrieu, J. Arcamone, E. Ollier
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a954addef7e27e3dfae349b36fd38937
https://doi.org/10.1109/iedm19574.2021.9720671
https://doi.org/10.1109/iedm19574.2021.9720671
Autor:
R. Kom Kammeugne, C. Leroux, T. Mota Frutuoso, J. Cluzel, L. Vauche, C. Le Royer, R. Gwoziecki, X. Garros, F. Gaillard, M. Charles, E. Bano, G. Ghibaudo
Publikováno v:
ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6d94ca0e60d5a44939ec6f9faa39f86
https://doi.org/10.1109/essderc53440.2021.9631820
https://doi.org/10.1109/essderc53440.2021.9631820
Autor:
Xavier Garros, Jose Lugo-Alvarez, Laurent Brunet, Perrine Batude, Christoforos G. Theodorou, P. Sideris, Philippe Ferrari, C. Fenouille-Beranger, T. Mota Frutuoso, F. Gaillard
Publikováno v:
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
IEEE Transactions on Electron Devices, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
IEEE Transactions on Electron Devices, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GH
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::623ed3653c9c7d850202b6198472443c
https://hal.archives-ouvertes.fr/hal-03260955
https://hal.archives-ouvertes.fr/hal-03260955
Autor:
F. Gaillard, C. Fenouillet-Beranger, X. Garros, Joris Lacord, Jose Lugo-Alvarez, Louis Gerrer, M. Casse, Philippe Ferrari, Laurent Brunet, E. Catapano, Francois Andrieu, T. Mota Frutuoso
Publikováno v:
IRPS
The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~1013/cm2) are identified on the interface between the spacer oxide and the silicon film using Terman'
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b798b8f9f057b1cb27f5e46793857d71
https://doi.org/10.1109/irps46558.2021.9405107
https://doi.org/10.1109/irps46558.2021.9405107
Conference
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Akademický článek
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Conference
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