Zobrazeno 1 - 10
of 120
pro vyhledávání: '"T. Kirihata"'
Akademický článek
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Autor:
Norman Robson, Darren L. Anand, L. Jiang, E.H. Schroeder, Moy Danny, Robert Katz, Edmund Banghart, Faraz Khan, T. Kirihata
Publikováno v:
2019 Symposium on VLSI Technology.
Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adder
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::feb0f7f64f01db019b2fd3aeced48e57
https://doi.org/10.23919/vlsit.2019.8776510
https://doi.org/10.23919/vlsit.2019.8776510
Autor:
J. Pape, Robert Katz, Y. Mamy Randriamihaja, B. Parameshwaran, T. Kirihata, William McMahon, Z. Chbili, Norman Robson, Darren L. Anand, Alberto Cestero, Subramanian S. Iyer, Moy Danny, Andreas Kerber
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
Ramped programming optimization is investigated in order to limit the risk of gate oxide breakdown (BD) during the programming of a Multi-Time Programmable Memory. Optimization of the programming ramp rate has been proven to be beneficial at both dev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36d8440bde8c16d360dc096e7aa88b8f
https://doi.org/10.1109/irps.2017.7936386
https://doi.org/10.1109/irps.2017.7936386
Akademický článek
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Akademický článek
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Autor:
X. Chen, Derek H. Leu, D. Lea, T. Kirihata, Faraz Khan, J. B. Johnson, Dan Moy, Sami Rosenblatt, Norman Robson, Subramanian S. Iyer, Dimitris P. Ioannou, G. LaRosa, C. Kothandaraman
Publikováno v:
IRPS
We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72bbefa7cd94621b4282e9a2037e2073
https://doi.org/10.1109/irps.2015.7112816
https://doi.org/10.1109/irps.2015.7112816
Autor:
David R. Hanson, Paul C. Parries, Norman Robson, Subramanian S. Iyer, T. Kirihata, Babar A. Khan, M. Wordeman, Geng Wang, J. Griesemer, Gregory J. Fredeman, R. Rajeevakumar, Hoki Kim, John W. Golz, Alberto Cestero
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:1377-1387
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4269daa702a398822bdfe832742483a4
https://doi.org/10.1109/jssc.2005.848019
https://doi.org/10.1109/jssc.2005.848019
Autor:
M. Wordeman, Gerhard Mueller, Gerd Frankowsky, Dmitry G. Netis, David R. Hanson, Daniel W. Storaska, Oliver Weinfurtner, Johann Alsmeier, L. Hsu, Carl J. Radens, John K. DeBrosse, A. Frey, Hartmund Terletzki, S. Panaroni, K.P. Guay, W. Weber, Armin M. Reith, Heinz Hoenigschmid, Brian L. Ji, Gabriel Daniel, T. Kirihata
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:713-718
A 7F/sup 2/ DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 /spl mu/m technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty-free inter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c71d841732e96154e93df33617c40c31
https://doi.org/10.1109/4.841498
https://doi.org/10.1109/4.841498
Autor:
K.P. Guay, Gerd Frankowsky, Armin M. Reith, Hartmund Terletzki, Brian L. Ji, M. Wordeman, Dmitry G. Netis, Gerhard Mueller, M.A. Hug, David R. Hanson, Gabriel Daniel, Oliver Weinfurtner, L. Hsu, J.M. Ross, M. Selz, T. Kirihata, D.W. Sotraska, P. Poechmueller, H. Hoenigschmid
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:1580-1588
A 390-mm/sup 2/, 16-bank, 1-Gb, double-data-rate (DDR) synchronous dynamic random access memory (SDRAM) has been fabricated in fully planarized 0.175-/spl mu/m, 8F/sup 2/ trench cell technology. The 1-Gb SDRAM employs a hybrid bitline architecture wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb8566d171bdb3229e06ef6d46101f74
https://doi.org/10.1109/4.799866
https://doi.org/10.1109/4.799866
Autor:
Oliver Weinfurtner, M. Selz, W. Ellis, Kohji Hosokawa, K.-P. Pfefferl, O. Kiehl, T. Kirihata, J. DeBrosse, Hing Wong, M. Gall, J.-M. Dortu, Brian L. Ji, M. Wordeman, Hartmund Terletzki
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1711-1719
A 220-mm/sup 2/, 256-Mb SDRAM has been fabricated in fully planarized 0.22-/spl mu/m CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7403f66a2c08360414164352d88edad4
https://doi.org/10.1109/4.726565
https://doi.org/10.1109/4.726565