Zobrazeno 1 - 6
of 6
pro vyhledávání: '"T. J. McPherson"'
Publikováno v:
IBM Journal of Research and Development. 43:651-660
System performance management is a broad category of techniques that cover all aspects of obtaining maximum performance or speed from a given design. Items such as sorting methodology, critical path improvements, semiconductor line optimization, powe
Autor:
Patrick M. Williams, Allan H. Dansky, T. J. McPherson, Timothy G. McNamara, David A. Webber, Dale Eugene Hoffman, Michael Alexander Bowen, Robert M. Averill, Gregory A. Northrop, Howard H. Smith, L. Sigal, S. A. McCabe, M. Mayo, Peter J. Camporese, R. F. Hatch, K. G. Barkley Iii
Publikováno v:
IBM Journal of Research and Development. 43:681-706
Publikováno v:
IBM Journal of Research and Development. 41:475-488
The S/390® floating-point unit (FPU) on the fourth-generation (G4) CMOS microprocessor chip has been implemented in a CMOS technology with a 0.20-µm effective channel length and has been demonstrated at more than 400 MHz. The microprocessor chip is
Autor:
Brian W. Curran, Y.-H. Chan, S. Carey, Patrick J. Meaney, M. Mayo, L. Sigal, Guenter Mayer, Michael Fee, Lee Evan Eisen, Eric M. Schwarz, Pak-Kin Mak, D. Malone, Frank Malgioglio, Howard H. Smith, T. J. McPherson, Huajun Wen, Thomas Strach, Michael H. Wood, William V. Huott, M. J. Saccamango, James D. Warnock, S. Weitzel, Yuen H. Chan, David L. Rude, R. Averill, Donald W. Plass, Charles F. Webb
Publikováno v:
ISSCC
The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm des
Autor:
Barry Watson Krumm, Gregory A. Northrop, Y.H. Chan, C. Krygowski, Timothy G. McNamara, T. J. McPherson, Eric M. Schwarz, John Stephen Liptay, M. Check, Dale Eugene Hoffman, D. Webber, M. Mayo, K. Barkley, Y.-H. Chan, S. Carey, R. Averill, Charles F. Webb, William V. Huott, L.S.T. Siegel, Patrick M. Williams
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and an IEEE compliant binary floating-point. The microprocessor operates at 600 MHz a
Autor:
M. Mayo, S. Carey, Dale Eugene Hoffman, Yuen Chan, T. Koprowski, Brian W. Curran, R. Crea, Yiu-Hing Chan, F. Tanzi, Gregory A. Northrop, Patrick M. Williams, R. Clemen, Howard H. Smith, Peter J. Camporese, T. J. McPherson, L. Sigal
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The first 64 b S/390 microprocessor implemented in a 0.18 /spl mu/m, 7-level copper interconnect bulk CMOS process, runs operating system and applications at 1.1 GHz. The frequency is achieved with interconnect width and repeater optimization, select