Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Szu-Pang Mu"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:1675-1687
This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip’s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for
Publikováno v:
ITC-Asia
This paper presents a framework which can avoid the lengthy system test by utilizing machine-learning techniques to classify parts into different DVFS bins based on the results collected at CP and FT test only. The core machine-learning techniques in
Autor:
Yi-Ming Wang, Wen-Hsiang Chang, Szu-Pang Mu, Min-Hsiu Tsai, Ming-Tung Chang, Mango C.-T. Chao
Publikováno v:
ICCAD
In previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip's maximum operating frequency (F max ). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The plac
Autor:
Yen-Chih Chiu, Szu-Pang Mu, Chien-Hsueh Lin, Mango C.-T. Chao, Li-De Chen, Cheng-Hong Tsai, Wen-Hsiang Chang
Publikováno v:
ISPD
As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electro-migration (EM) constraints. This paper presents a design flow to generate a PDN that
Autor:
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango C.-T. Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai
Publikováno v:
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
Autor:
Szu-Pang Mu, Mango C.-T. Chao
Publikováno v:
VTS
This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuse