Zobrazeno 1 - 10
of 609
pro vyhledávání: '"Systemverilog"'
Autor:
Diana DRANGA
Publikováno v:
Revista Română de Informatică și Automatică, Vol 34, Iss 2, Pp 75-84 (2024)
As the production of electronics increases exponentially each year, the need for them to be able to function properly (according to the documentation) is critical. The functional verification process is a complex and time consuming step when deliveri
Externí odkaz:
https://doaj.org/article/275cb2f1f48e4f078e2480fe328e4813
Autor:
Chao Wang, Yicong Shao, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 5, Pp 387-397 (2024)
This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital
Externí odkaz:
https://doaj.org/article/e14a5a49011d436f864ed4023f14671e
Publikováno v:
IEEE Access, Vol 12, Pp 148143-148154 (2024)
In the dynamic fields of semiconductor design and digital system development, effective verification procedures are in high demand. In particular, functional verification is essential for space systems to guarantee mission success, prevent errors in
Externí odkaz:
https://doaj.org/article/1aae296cb300417ba773d2eae9fa2e2f
Autor:
Frank Bruno
Get started with FPGA programming using SystemVerilog, and develop real-world skills by building projects, including a calculator and a keyboardKey FeaturesExplore different FPGA usage methods and the FPGA tool flowLearn how to design, test, and impl
Publikováno v:
IEEE Access, Vol 11, Pp 79721-79738 (2023)
Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it’s one of the essential blocks in any Inte
Externí odkaz:
https://doaj.org/article/aef46a0fb20e495a9c6b91c8f2517044
Publikováno v:
International Journal of Electronics and Telecommunications, Vol vol. 68, Iss No 3, Pp 619-623 (2022)
A testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, envi
Externí odkaz:
https://doaj.org/article/a5aeebff8dff453180972b7700230d66