Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Swan Johanna M"'
Scaling Solder Micro-Bump Interconnect Down to $10\ \mu\mathrm{m}$ Pitch for Advanced 3D IC Packages
Autor:
Zhaozhi Li, Yoshihiro Tomita, Holly A. Sawyer, Swan Johanna M, Elsherbini Adel A, Shawna M. Liff, Pilin Liu
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
This paper discusses the efforts to shrink the micro-bump pitch to $20\ \mu\mathrm{m}$ and then $10\ \mu\mathrm{m}$ with solder micro-bumps for silicon-on-silicon 3D assembly by leveraging alternate solder diffusion barrier metals and tuning the asse
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1d2a58cfff223f710a85a9c78a780bc
https://doi.org/10.1109/ectc32696.2021.00082
https://doi.org/10.1109/ectc32696.2021.00082
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
This paper presents cold spray as a nascent semiconductor packaging capability with promising thermomechanical applications. Cold spray enables fast, low temperature, solid-state additive manufacturing of die backside coatings with near-bulk properti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3baff36ffaf1b36f672114386ea617f6
https://doi.org/10.1109/ectc32696.2021.00181
https://doi.org/10.1109/ectc32696.2021.00181
Autor:
Gerald S. Pasdast, Sathya Tiagaraj, Elsherbini Adel A, Swan Johanna M, Kimin Jun, Shawna M. Liff
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Die stacking enables significant performance leaps in computing capability and memory/processor integration. Conventional die stacking uses solder interconnects which suffer from several scaling limitations. A new die to die interconnect technology,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ff0bb0358f314e870764363ce01acfe
https://doi.org/10.1109/ectc32696.2021.00166
https://doi.org/10.1109/ectc32696.2021.00166
Autor:
Telesphor Kamgaing, Georgios C. Dogiamis, Swan Johanna M, Ruonan Han, J.W. Holloway, Darmawikarta Kristof, Elsherbini Adel A, Sri Ranga Sai Boyapati, Aleksandar Aleksov
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
RF substrate packages were built using organic dielectric layers with Copper (Cu) based interconnects employing lithographically defined vias as a new manufacturing paradigm for a semi-additive process flow. The package-based RF-to-THz structures ena
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2627e98f510195ae15fb5e3484ff77e9
https://doi.org/10.1109/iedm13553.2020.9372088
https://doi.org/10.1109/iedm13553.2020.9372088
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
We present a new packaging building block for 3D integrated circuits: Omni Directional Interconnect (ODI). It adds a new degree of freedom in packaging that enables combining the high bandwidth benefit of standard 3D stacking with the minimal die are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0d52c18f92ae1a24aba6efaebe50a6f
https://doi.org/10.1109/iedm19573.2019.8993659
https://doi.org/10.1109/iedm19573.2019.8993659
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
In this paper, a novel technology is presented in which organic substrate manufacturing is used to create sensors and actuators directly in the CPU package. The dielectric material surrounding some interconnect traces in the substrate is removed, all
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1dfd66e1ee2e9af8efe0e55cbd02dd6e
https://doi.org/10.1109/ectc.2017.18
https://doi.org/10.1109/ectc.2017.18
Autor:
Michael R. Bynum, Lakshman Krishnamurthy, Alexander Essaian, Torrey W. Frank, Vijay K. Nair, Swan Johanna M
Publikováno v:
RWS
This paper discusses design, fabrication and characterization of a 3D stacked small form factor (SFF) system-in-packages (SiPs) suitable for wearable electronics systems. In order to achieve very small size SiP, two SFF multi-chip packages were desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b97bbeccb54ab7970f2541180c33df7e
https://doi.org/10.1109/rws.2017.7885959
https://doi.org/10.1109/rws.2017.7885959
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
This paper reports on the design, fabrication and characterization of active die embedded ultra slim system-in-packages suitable for integrating RF and digital integrated circuits, and discrete components. Portable communication devices such as Ultra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3dd581c049e04f62c2009e2921b7b77
https://doi.org/10.1109/ectc.2014.6897456
https://doi.org/10.1109/ectc.2014.6897456
Publikováno v:
13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.
With the continuous scaling of low k dielectric in multicore processors, the intrinsic CTE mismatch between a Si die (CTE: 2.3 ppm/°C) and an organic substrate (16–18 ppm/°C) brings a susceptibility for more failures. There are limited successes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cddc3470d98cf44686354b703ffd40c4
https://doi.org/10.1109/itherm.2012.6231426
https://doi.org/10.1109/itherm.2012.6231426
Publikováno v:
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.
Silicon Bridge is a dense multichip packaging architecture that enables high die-to-die interconnect density and corresponding applications. We describe the basic ideas of the concept, discuss density in the die-to-die interconnect context, and repor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34ad08099f1abe7ac98e03c7c0d5c43a
https://doi.org/10.1109/epeps.2011.6100196
https://doi.org/10.1109/epeps.2011.6100196