Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Svetlana Saburova"'
Publikováno v:
Applied Sciences, Vol 13, Iss 18, p 10200 (2023)
This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of outp
Externí odkaz:
https://doaj.org/article/6cbb8e7f60584ed0b5f715218f462082
Publikováno v:
Electronics; Volume 11; Issue 6; Pages: 950
One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (
Publikováno v:
Electronics
Volume 10
Issue 8
Electronics, Vol 10, Iss 901, p 901 (2021)
Volume 10
Issue 8
Electronics, Vol 10, Iss 901, p 901 (2021)
Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most imp
Publikováno v:
Electronics
Volume 9
Issue 11
Electronics, Vol 9, Iss 1859, p 1859 (2020)
Volume 9
Issue 11
Electronics, Vol 9, Iss 1859, p 1859 (2020)
Contemporary digital systems include many varying sequential blocks. In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. In many cases, the performance is the most important characteri
Autor:
Svetlana Saburova, Olga Kadatskaya
Publikováno v:
2014 First International Scientific-Practical Conference Problems of Infocommunications Science and Technology.