Zobrazeno 1 - 10
of 228
pro vyhledávání: '"Susumu Takeda"'
Autor:
Susumu Takeda
Publikováno v:
Journal of Smart Processing. 9:56-62
Publikováno v:
VLSI Circuits
Recently MRAM technologies have been intensively developed. This paper describes novel solutions using advanced MRAM for near future computing applications. Three beneficial applications with MRAM are presented: energy saving, data reliability and pe
Autor:
B. Altansargai, Yuichi Ohsawa, Y. Kato, S. Fujita, Satoshi Shirotori, Tomoaki Inokuchi, Susumu Takeda, Atsushi Kurobe, Soichi Oikawa, Mariko Shimizu, K. Koi, Kazutaka Ikegami, Hiroaki Yoda, Hideyuki Sugiyama, Naoharu Shimomura, Satoshi Takaya
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
We report a novel convolutional neural network (CNN) accelerator utilizing “voltage control spintronics memory” (VoCSM). High throughput processing is achieved by high speed in-“nonvolatile memory”-computation using high density VoCSM array.
Publikováno v:
VLSI-DAT
Among various kinds of nonvolatile memory developed, spin torque transfer (STT)-MRAM has the highest write access speed and highest endurance (close to practically unlimited endurance). Hence, embedded (e-) STT-MRAM can cover various kinds of working
Autor:
Shigeru Hidaka, Hitoshi Sasaki, Khoji Shimizume, Kaname Kishino, Hiroyuki Fujiki, Yasutaka Amagai, Susumu Takeda
Publikováno v:
IEEJ Transactions on Electrical and Electronic Engineering. 8:101-104
A new multijunction thermal converter (MJTC) for precision AC–DC transfer standard has been developed. A U-shaped heater pattern was sputter-deposited onto an AlN plate in order to reduce thermoelectric effect, which causes the frequency-independen
Autor:
Eishi Arima, Takashi Nakada, Shinobu Miwa, Shinobu Fujita, Susumu Takeda, Kumiko Nomura, Hiroki Noguchi, Hiroshi Nakamura
Publikováno v:
2015 International SoC Design Conference (ISOCC).
This paper describes state-of-the-art STT-MRAM, which can drastically save energy consumption dissipated in cache memory system compared with conventional SRAM-based ones. This paper also presents how to build cache memory hierarchy with both the sta
Autor:
Hiroki Noguchi, Hiroshi Nakamura, Shinobu Miwa, Takashi Nakada, Shinobu Fujita, Eishi Arima, Susumu Takeda
Publikováno v:
ICCD
Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer f
Autor:
Susumu Takeda
Publikováno v:
Journal of Indian and Buddhist Studies (Indogaku Bukkyogaku Kenkyu). 60:167-173
Publikováno v:
2015 IEEE International Memory Workshop (IMW).
This paper presents fast and low-power embedded nonvolatile memory technologies and circuit designs based on perpendicular STT-MRAM. Future prospects of applications are also discussed.
Publikováno v:
ISIC
This paper presents novel ultra-low power processor based on “Normally-off (N-off)” architecture, on which processors can remain in “off state” even during a short standby state. To realize “N-off” for high-performance (HP-) processors, w