Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Susumu Kohyama"'
Publikováno v:
2010 Symposium on VLSI Circuits.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::112281a7578a7849f624b246a6a71718
https://doi.org/10.1109/vlsic.2010.5560247
https://doi.org/10.1109/vlsic.2010.5560247
Autor:
Susumu Kohyama
Publikováno v:
Proceedings of 1994 VLSI Technology Symposium.
Continuing device miniaturization results in higher packing density and higher fabrication cost, thus requires high ROI products utilizing complex design capability. Usually complex design requires higher abstraction in order to cope with the design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4969cfd98aa6604d8efd63461fe1e523
https://doi.org/10.1109/vlsit.1994.324404
https://doi.org/10.1109/vlsit.1994.324404
Publikováno v:
IEEE Transactions on Electron Devices. 32:217-223
High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously result
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb5778f6931462ece843ded4cc33525c
https://doi.org/10.1109/t-ed.1985.21932
https://doi.org/10.1109/t-ed.1985.21932
Publikováno v:
IEEE Journal of Solid-State Circuits. 20:137-143
High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc7ef6235fbef76863fff29ba8376a2a
https://doi.org/10.1109/jssc.1985.1052286
https://doi.org/10.1109/jssc.1985.1052286
Autor:
Kiyofumi Ochii, Susumu Kohyama, Kazuhiko Hashimoto, T. Kondo, Hiroshi Yasuda, H. Nozawa, M. Masuda
Publikováno v:
IEEE Journal of Solid-State Circuits. 17:798-803
A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a70b8916bb50459fd24b97c453302079
https://doi.org/10.1109/jssc.1982.1051821
https://doi.org/10.1109/jssc.1982.1051821
Publikováno v:
IEEE Journal of Solid-State Circuits. 17:804-809
A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral ci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f636d67ba1033bfdf044e02d9ce5e6a3
https://doi.org/10.1109/jssc.1982.1051822
https://doi.org/10.1109/jssc.1982.1051822
Autor:
Susumu Kohyama, Kazunori Ohuchi
Publikováno v:
The Journal of the Institute of Television Engineers of Japan. 29:680-687
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c3ba735e3a0ef5ae8c1248ce0be187f
https://doi.org/10.3169/itej1954.29.680
https://doi.org/10.3169/itej1954.29.680
Publikováno v:
IEEE Transactions on Electron Devices. 31:1413-1419
A new EPROM named SEPROM, based on a modified SEPOX process, is proposed and evaluated. The SEPROM offers a process compatibility to logic LSI's with higher packing density, since the area of the second gate oxide is equal to that of the first gate o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c004605096322d943fe8ec0d8942090b
https://doi.org/10.1109/t-ed.1984.21726
https://doi.org/10.1109/t-ed.1984.21726
Publikováno v:
Applied Physics Letters. 35:21-23
Polycrystalline silicon layers heavily doped with phosphorus or arsenic were irradiated with a Nd : YAG pulsed laser beam. A 40–50% reduction in sheet resistivity was obtained by laser annealing. However, during subsequent heat treatments the resis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::173a06c1d5179896d2c87fc02ae03d0c
https://doi.org/10.1063/1.90917
https://doi.org/10.1063/1.90917
Autor:
Susumu Kohyama, Junichi Matsunaga
Publikováno v:
Applied Physics Letters. 33:335-337
Impact‐ionization current during saturation mode operation is widely known in MOS devices. Although not noted in previous work, minority carriers also may be observed in the substrate, together with hole current. These minority carriers can degrade
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8260c6710fad3347f43bcfad7566db35
https://doi.org/10.1063/1.90361
https://doi.org/10.1063/1.90361