Zobrazeno 1 - 10
of 54
pro vyhledávání: '"Susana Paton"'
Publikováno v:
Sensors, Vol 22, Iss 19, p 7458 (2022)
Digital and smart sensors are commonly implemented using multi-bit ΣΔ Modulators. Undesired signals can be present at the ADC input, such as low-frequency signals with medium or high amplitude, as a consequence of mechanical artifacts in the MEMS a
Externí odkaz:
https://doaj.org/article/2e90b7fea3444ea09357e61f8b109a02
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 70:870-874
Publikováno v:
IEEE Sensors Journal. 23:3005-3019
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:920-929
This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma–delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sam
Autor:
Susana Paton, Leidy Mabel Alvero-Gonzalez, Luis Hernandez, Eric Gutierrez, Victor Medina, Vahur Kampus
Publikováno v:
e-Archivo. Repositorio Institucional de la Universidad Carlos III de Madrid
instname
Electronics, Vol 10, Iss 1408, p 1408 (2021)
Electronics
Volume 10
Issue 12
instname
Electronics, Vol 10, Iss 1408, p 1408 (2021)
Electronics
Volume 10
Issue 12
This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors conn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d25029b08a0264a8e86f9ae4f912fc0d
http://hdl.handle.net/10016/34326
http://hdl.handle.net/10016/34326
Autor:
Pablo Vera, Susana Paton
Publikováno v:
DCIS
Discrete time Σ∆ modulators habitually use a multi-level uniform quantizer (UQ); with this type of quantizer the maximum resolution is reached around full scale and system stability is improved. In this work, we propose the use of a multi-level no
Publikováno v:
ISCAS
This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma-delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampl
Publikováno v:
ISCAS
Scopus-Elsevier
Scopus-Elsevier
The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that
Publikováno v:
ICECS
This work presents the architectural concept and circuit simulation of a third order VCO-based Continuous-Time Sigma-Delta Modulator. The loop filter has a mixed mode resonator built with an RC-OTA PI element and a VCO-based integrator coupled throug