Zobrazeno 1 - 10
of 30
pro vyhledávání: '"Suresh Uppal"'
Autor:
Xiaoli He, Shimpei Yamaguchi, Owen Hu, Zeynel Bayindir, Chloe Yong, Srikanth Samavedam, Hyuck Soo Yang, Dong Kyun Sohn, Suresh Uppal, Manoj Joshi, Purushothaman Srinivasan, Dongil Choi
Publikováno v:
Microelectronics Reliability. 72:80-84
In this work, we investigated the effect of so-called WF (Work Function) setting anneal (high temperature annealing on TiN/HfO 2 stack) on gate stack properties. It was found that intermixed layer created in-between TiN and HfO 2 during WF setting an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9457a506b54889f3e120aa462ed7c14
https://doi.org/10.1016/j.microrel.2017.04.004
https://doi.org/10.1016/j.microrel.2017.04.004
Autor:
Suresh Uppal, Talapady Srivatsa Bhat, Shimpei Yamaguchi, Hui Zhan, Xiaobo Chen, Jianghu Yan, Shashidhar Shintri, Suresh Regonda, Yong Jun Shi, Srikanth Samavedam, Qi Yi, Hsien-Ching Lo, Yan Ping Shen, Dongil Choi, Owen Hu, Manoj Joshi, Jianwei Peng, Chloe Yong, Hong Wei, Baofu Zhu
Publikováno v:
ECS Journal of Solid State Science and Technology. 6:N137-N141
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39395ed3644bd0dbf5ce4571033e3367
https://doi.org/10.1149/2.0011709jss
https://doi.org/10.1149/2.0011709jss
Autor:
R. Krishnan, Pei Zhao, Yue Hu, Dongil Choi, El Mehdi Bazizi, Xiaoli He, Jody A. Fronheiser, Rick Carter, Zhaoying Hu, K. Tabakman, Ashish Kumar Jha, Srikanth Samavedam, Hong Yu, Suresh Uppal, Owen Hu, Jae Gon Lee, D. K. Sohn, Ryan Sporer, Liqiao Qin, Xusheng Wu
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width (W) scaling on logic and SRAM device characteristics. TCAD analysis is use
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::330c88b607312709dc7d0dbf8aac90bb
https://doi.org/10.1109/iedm.2017.8268427
https://doi.org/10.1109/iedm.2017.8268427
Device reliability metric for end-of-life performance optimization based on circuit level assessment
Autor:
Sandhya Chandrashekhar, Dhruv Singh, Prashanth Paramahans Manik, Andreas Kerber, Rakesh Ranjan, Fernando Guarin, B. Parameshwaran, P. Paliwoda, T. Nigam, S. Cimino, Z. Chbili, Jeyaraj Antony Johnson, Suresh Uppal, Purushothaman Srinivasan, M.-I. Mahmud
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
Performance enhancement is critical for offering competitive CMOS solutions for advanced technology nodes. To fully leverage performance enhancement elements the device reliability impact needs to be comprehended on the CMOS circuits like SRAM and ri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9998d73d683a636c45903f8f71a0713a
https://doi.org/10.1109/irps.2017.7936263
https://doi.org/10.1109/irps.2017.7936263
Autor:
Andreas Kerber, Mahadeva Iyer Natarajan, B. Parameshwaran, C. LaRow, T. Nigam, Rakesh Ranjan, H. Yu, Suresh Uppal
Publikováno v:
2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).
The impact of source/drain e-SiGe process engineering on time dependent dielectric breakdown (TDDB) on core PFETs fabricated with bulk FinFET technology is evaluated. It is observed that thicker e-SiGe buffer layer improves the PFETs TDDB. Electrical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1015de3fa35b1db8c87395731be5b19
https://doi.org/10.1109/edtm.2017.7947492
https://doi.org/10.1109/edtm.2017.7947492
Autor:
X. Zhang, Manfred Eller, Mitsuhiro Togo, Murali Kota, T. Shimizu, Suraj K. Patil, Dina H. Triyoso, Suresh Uppal, Srikanth Samavedam, E. C. Silva, S. Dag, J. Lian, W. H. Tong, Y. Mamy Randriamihja
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
A novel N/PFET threshold voltage (Vt) control scheme was developed for aggressive gate scaling. TiN plasma nitridation reduces absolute Vt by 100mV for both NFETs and PFETs at the same time without photolithography step increase and performance or re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f11a24b464e6077f496a6ebdfd20dbd
https://doi.org/10.1109/vlsit.2016.7573436
https://doi.org/10.1109/vlsit.2016.7573436
Autor:
Anthony O'Neill, Hiran Ramakrishnan, Enrique Escobedo-Cousin, Sarah H. Olsen, Suresh Uppal, Y.L. Tsang, Sanatan Chattopadhyay
Publikováno v:
IEEE Transactions on Electron Devices. 54:3040-3048
In this paper, an analytical model of threshold voltage for globally strained Si/SiGe CMOS devices using a dual channel architecture is proposed. Since band parameters modify , they are calculated and generalized for different Ge contents in a film g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71ad3c87e88fb997b4eb00f56c52c115
https://doi.org/10.1109/ted.2007.907190
https://doi.org/10.1109/ted.2007.907190
Autor:
Suresh Uppal
Publikováno v:
2015 IEEE International Integrated Reliability Workshop (IIRW).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92a44d0b91ab7ab852207f4812716c34
https://doi.org/10.1109/iirw.2015.7437094
https://doi.org/10.1109/iirw.2015.7437094
Autor:
Per-Erik Hellström, Anthony O'Neill, JB Varzgar, Mikael Östling, Erich Kasper, Klara Lyutovich, Suresh Uppal, Y.L. Tsang, Sarah H. Olsen, Mehdi Kanoun, Sanatan Chattopadhyay, Enrique Escobedo-Cousins, Jonas Edholm, Michael Oehme
Publikováno v:
Materials Science and Engineering: B. 135:203-206
The reliability of gate oxides on bulk Si and strained Si (s-Si) has been evaluated using constant voltage stressing (CVS) to investigate their breakdown characteristics. The s-Si architectures exh ...
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a34e5c9debbf6e03fed5df7cde1c4ac
https://doi.org/10.1016/j.mseb.2006.08.005
https://doi.org/10.1016/j.mseb.2006.08.005
Autor:
Benjamin Colombeau, Arthur F. W. Willoughby, M. S. A. Karunaratne, Janet M. Bonar, Suresh Uppal, E. Lampin, Peter Pichler, Alain Claverie, Filadelfo Cristiano, Silke Paul, Christophe J Ortiz, Nick E. B. Cowern, Wilfried Lerch
Publikováno v:
Physica Scripta. :89-96
A quantitative description of the transient diffusion and activation of boron during post-implantation annealing steps is one of the most challenging tasks in the simulation of silicon doping processes. In industrially relevant situations, simulation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe69802d8ce63c6b7ed3c6b3cb841b61
https://doi.org/10.1088/0031-8949/2006/t126/021
https://doi.org/10.1088/0031-8949/2006/t126/021