Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Supratim Subhra Das"'
Publikováno v:
2023 IEEE Devices for Integrated Circuit (DevIC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e073080cca6cf893c072ea68ca159c6
https://doi.org/10.1109/devic57758.2023.10134990
https://doi.org/10.1109/devic57758.2023.10134990
Autor:
Supratim Subhra Das, Md. Asraful Sekh
Publikováno v:
ICT Analysis and Applications ISBN: 9789811952234
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::962fc2d0244b75d40fb8fe150f35e384
https://doi.org/10.1007/978-981-19-5224-1_28
https://doi.org/10.1007/978-981-19-5224-1_28
Autor:
Supratim Subhra Das
Publikováno v:
Journal of The Institution of Engineers (India): Series B. 103:101-105
In this paper, an analysis of Fin thickness variation on device performance of SiGe channel FinFET on SOI technology is reported. For a double gate n-channel FinFET with a gate length of 32 nm and Fin height of 60 nm, thickness of fin is varied from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e806990ee34401e643e64fa36b0e3f9c
https://doi.org/10.1007/s40031-021-00641-2
https://doi.org/10.1007/s40031-021-00641-2
Autor:
Supratim Subhra Das
Publikováno v:
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS).
A doped double gate uni-junction silicon-based novel Tunnel Field Effect Transistor (TFET) structure is proposed that exhibits lower subthreshold slope (10 mV/decade) and better ON to OFF current ratio (I on /I off is in order of 107 at low supply vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcf6cafd4d11ec7d0a50bc3c3c6c3d7a
https://doi.org/10.1109/vlsidcs47293.2020.9179745
https://doi.org/10.1109/vlsidcs47293.2020.9179745
Autor:
Supratim Subhra Das
Publikováno v:
2018 IEEE Electron Devices Kolkata Conference (EDKCON).
This paper proposes a novel work function engineered dual material gate Tunnel FET structure. The proposed device has similar structural configuration with that of a normal double gate (DG) TFET and therefore feasible in aspect of fabrication. The pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3eb496c45fb51d5ea311cd035d82f6d
https://doi.org/10.1109/edkcon.2018.8770435
https://doi.org/10.1109/edkcon.2018.8770435