Zobrazeno 1 - 10
of 12
pro vyhledávání: '"SuperSPARC"'
Publikováno v:
Proceedings of the IEEE. 91:1038-1054
The architecture of tools for the determination of worst case execution times (WCETs) as well as the precision of the results of WCET analyses strongly depend on the architecture of the employed processor. The cache replacement strategy influences th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b762628058e9d20af3a2cc5e89186cca
https://doi.org/10.1109/jproc.2003.814618
https://doi.org/10.1109/jproc.2003.814618
Publikováno v:
Proceedings of the International Conference on Multichip Modules.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::699fba5970641520e77f83b9153b42a4
https://doi.org/10.1109/icmcm.1994.753595
https://doi.org/10.1109/icmcm.1994.753595
Autor:
G. Blanck, S. Krueger
Publikováno v:
Digest of Papers COMPCON Spring 1992.
The SuperSPARC microprocessor is a highly integrated, high-performance superscalar SPARC version 8 compatible microprocessor. The authors provide an overview of its internal operation and capabilities. The processor contains an integer unit, a double
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79be18be1e3bfc23405ba9a440958d92
https://doi.org/10.1109/cmpcon.1992.186699
https://doi.org/10.1109/cmpcon.1992.186699
Autor:
H. Davidson, C.W. Eichelberger
Publikováno v:
Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.
A program to develop a Viking SuperSparc AMCM is discussed. The program is structured not only to provide a prototype module, but also to resolve key infrastructure issues associated with volume production of the module. The AMCM technology was chose
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5358cdaf41169ab6817806d5004f7f6a
https://doi.org/10.1109/mcmc.1993.302157
https://doi.org/10.1109/mcmc.1993.302157
Autor:
R. Patel, K. Yarlagadda
Publikováno v:
Proceedings of IEEE International Test Conference - (ITC).
The Texas Instruments SuperSPARC is a high performance BiCMOS superscalar microprocessor containing 3.1 M transistors. This paper describes the testability features of this highly integrated processor aiming towards achieving a highly manufacturable
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd2073e409e7d1a0e31610357b42a75c
https://doi.org/10.1109/test.1993.470625
https://doi.org/10.1109/test.1993.470625
Publikováno v:
Proceedings 1997 International Conference on Multichip Modules.
In this paper, the results of a cost model study comparing Diffusion Patterning/sup TM/, Fodel(R), and Green Tape/sup TM/ implementations of a 10 chip Viking SuperSPARC/sup TM/ Module is reviewed. Results include a discussion of key assumptions and a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::adbedb7af866ddf6b5de49fe375e564d
https://doi.org/10.1109/icmcm.1997.581147
https://doi.org/10.1109/icmcm.1997.581147
Publikováno v:
HICSS (2)
Presents a method for determining the cache performance of the loop nests in a program. The cache-miss data are produced by simulating the loop nest execution on an architecturally parameterized cache simulator. We show that the cache-miss rates are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a984b009a88b5812a2a175f8cca0fe5
https://doi.org/10.1109/hicss.1995.375473
https://doi.org/10.1109/hicss.1995.375473
Publikováno v:
ITC
This paper describes a structured design-for-debug methodology that provides observability throughout an entire chip. It makes use of existing design-for-testability (DFT) features on the chip and is part of the overall DFT strategy. The implementati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41892f0626917f68bb9a4ea32b18842f
https://doi.org/10.1109/test.1995.529831
https://doi.org/10.1109/test.1995.529831
Autor:
Jörn Schneider, Christian Ferdinand
Publikováno v:
Workshop on Languages, Compilers, and Tools for Embedded Systems
For real time systems not only the logical function is important but also the timing behavior, e. g. hard real time systems must react inside their deadlines. To guarantee this it is necessary to know upper bounds for the worst case execution times (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2140b1944939b28182cb7ade06d6c924
https://doi.org/10.1145/314403.314432
https://doi.org/10.1145/314403.314432
Publikováno v:
Processor Architecture ISBN: 9783540647980
Superscalar processors started to conquer the microprocessor market at the beginning of the 1990s with dual-issue processors. The principal motivation was to overcome the single issue of scalar RISC processors by providing the facility to fetch, deco
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::515e5b4103698fa4330531cfb6c9678c
https://doi.org/10.1007/978-3-642-58589-0_4
https://doi.org/10.1007/978-3-642-58589-0_4
