Zobrazeno 1 - 10
of 662
pro vyhledávání: '"SuperSPARC"'
Autor:
G. Blanck, S. Krueger
Publikováno v:
Digest of Papers COMPCON Spring 1992.
The SuperSPARC microprocessor is a highly integrated, high-performance superscalar SPARC version 8 compatible microprocessor. The authors provide an overview of its internal operation and capabilities. The processor contains an integer unit, a double
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79be18be1e3bfc23405ba9a440958d92
https://doi.org/10.1109/cmpcon.1992.186699
https://doi.org/10.1109/cmpcon.1992.186699
Publikováno v:
Proceedings of the International Conference on Multichip Modules.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::699fba5970641520e77f83b9153b42a4
https://doi.org/10.1109/icmcm.1994.753595
https://doi.org/10.1109/icmcm.1994.753595
Autor:
H. Davidson, C.W. Eichelberger
Publikováno v:
Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.
A program to develop a Viking SuperSparc AMCM is discussed. The program is structured not only to provide a prototype module, but also to resolve key infrastructure issues associated with volume production of the module. The AMCM technology was chose
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5358cdaf41169ab6817806d5004f7f6a
https://doi.org/10.1109/mcmc.1993.302157
https://doi.org/10.1109/mcmc.1993.302157
Autor:
R. Patel, K. Yarlagadda
Publikováno v:
Proceedings of IEEE International Test Conference - (ITC).
The Texas Instruments SuperSPARC is a high performance BiCMOS superscalar microprocessor containing 3.1 M transistors. This paper describes the testability features of this highly integrated processor aiming towards achieving a highly manufacturable
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd2073e409e7d1a0e31610357b42a75c
https://doi.org/10.1109/test.1993.470625
https://doi.org/10.1109/test.1993.470625
Publikováno v:
ITC
This paper describes a structured design-for-debug methodology that provides observability throughout an entire chip. It makes use of existing design-for-testability (DFT) features on the chip and is part of the overall DFT strategy. The implementati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41892f0626917f68bb9a4ea32b18842f
https://doi.org/10.1109/test.1995.529831
https://doi.org/10.1109/test.1995.529831
Autor:
K. Bhabuthmal, H. Hao
Publikováno v:
ICCD
This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f0bd4ed55d8132da629c57e0ccb1ac6
https://doi.org/10.1109/iccd.1995.528800
https://doi.org/10.1109/iccd.1995.528800
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (p. 119-120).
by Melissa C. Kwok.
M.S.
Includes bibliographical references (p. 119-120).
by Melissa C. Kwok.
M.S.
Externí odkaz:
http://hdl.handle.net/1721.1/36001
Publikováno v:
[Rapport de recherche] RR-1836, INRIA. 1993
Disponible dans les fichiers attachés à ce document
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::aa6bc28f9108069c74302a02d4f2c50e
https://hal.inria.fr/inria-00077190/file/RR-1836.pdf
https://hal.inria.fr/inria-00077190/file/RR-1836.pdf
Conference
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