Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Supamas Sirichotiyakul"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22:1188-1203
Noise simulators and noise avoidance tools are playing an increasingly critical role in the design of deep submicron circuits. However, noise estimates produced by these simulators are often very pessimistic. For large, high-performance industrial IC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::952af5ba500ce9bc5e89bee7b02a48f5
https://doi.org/10.1109/tcad.2003.816212
https://doi.org/10.1109/tcad.2003.816212
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11:157-166
In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross-coupling capacita
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a220cf23bd26dbcfb802a52ec8f6d3b1
https://doi.org/10.1109/tvlsi.2002.808448
https://doi.org/10.1109/tvlsi.2002.808448
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10:79-90
Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eae8afeb0d19d4e190368cd6129c3f17
https://doi.org/10.1109/92.994980
https://doi.org/10.1109/92.994980
Autor:
Jingyan Zuo, Tim Edwards, Rajendran Panda, Chanhee Oh, David Blaauw, Abhijit Dharchoudhury, Supamas Sirichotiyakul
Publikováno v:
DAC
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of "dominant lea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::86b6c1c11873e158bf96e445a076ce31
https://doi.org/10.1109/dac.1999.781356
https://doi.org/10.1109/dac.1999.781356
Autor:
Vladimir Zolotov, Supamas Sirichotiyakul, Ibrahim N. Hajj, Jingyan Zuo, Rafi Levy, M. Becer, David Blaauw, Chanhee Oh
Publikováno v:
ISQED
As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures that can be caused by coupling noise. In this paper, we present a global driver sizing tool wh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d0c7105f2b3f1d4a4094081c1cb5872
https://doi.org/10.1109/isqed.2001.915221
https://doi.org/10.1109/isqed.2001.915221
Autor:
Rafi Levy, A. Grinshpon, Vladimir Zolotov, Chanhee Oh, Supamas Sirichotiyakul, M. Becer, David Blaauw, Rajendran Panda
Publikováno v:
ICCAD
Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor ne
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2c96dbad84eae67dbdbf2333f011e9fe
https://doi.org/10.1145/774572.774659
https://doi.org/10.1145/774572.774659
Publikováno v:
DAC
The corruption of signals due to capacitive and inductive coupling of interconnects has become a significant problem in the design of deep submicron circuits (DSM). Noise simulators, based on worst-case assumptions, are overly pessimistic. As a resul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dda818c4423c1f5f9dd78940369cf122
https://doi.org/10.1109/dac.2002.1012706
https://doi.org/10.1109/dac.2002.1012706
Publikováno v:
DAC
In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross coupling capacita
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1595cef0455626416145adb5f785f94
https://doi.org/10.1145/378239.379054
https://doi.org/10.1145/378239.379054
Autor:
David Blaauw, Aurobindo Dasgupta, Chanlee Oh, Boaz Orshav, Rafi Levy, Amir Grinshpon, Supamas Sirichotiyakul, Vladimir Zolotov, Gabi Braca
Publikováno v:
DAC
Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e17ed5f7df870781e0a788ec6477f902
https://doi.org/10.1145/337292.337400
https://doi.org/10.1145/337292.337400
Autor:
Supamas Sirichotiyakul, Abhijit Dharchoudhury, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw
Publikováno v:
ISLPED
Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c92af09db16fc595b55197eed969d52
https://doi.org/10.1145/280756.280866
https://doi.org/10.1145/280756.280866