Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Suock Chung"'
Autor:
Kazumasa Sunouchi, Kyoung-Hwan Park, Guk-Cheon Kim, Kwang-Myoung Rho, Haruichi Kanaya, Suock Chung, Akihito Yamamoto, K. Noma, J. Y. Yi, Kenji Tsuchida, Tatsuya Kishi, Toshihiko Nagase, Mun-Haeng Lee, Yun-Seok Chun, S. J. Hong, Sung-Woong Chung, Hisato Oyamatsu, Hyeongon Kim, Jeongsoo Park, Masahisa Yoshikawa
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance co
Autor:
Hyun Sun Lee, Tae Jung Ha, Hoe Gwon Jung, Yoocharn Jeon, Sung Joo Hong, Kyu Sung Kim, Suock Chung, Wan Gee Kim, Hyeong Soo Kim, Lee Jung Hoon, Gary Gibson, Eung Rim Hwang, Jong Hee Yoo, Kyung Wan Kim, Kee Jeung Lee, Soo Gil Kim, Suk Pyo Song, Hyojin Kim, Seonghyun Kim, Ja Chun Ku, Jong Il Kim, Jong Chul Lee, Sang Hoon Cho, Jae-yeon Lee, Jong Ho Song, Jong Ho Kang, Beom-Yong Kim, Jung Ho Shin, Yong Taek Park
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and
Autor:
Suock Chung, Tae Hyung Park, Beom-Yong Kim, Byung Joon Choi, Kee Jeung Lee, Kyung-min Kim, Cheol Seong Hwang, Seul Ji Song, Soo Gil Kim, Hae Jin Kim
Publikováno v:
SCIENTIFIC REPORTS(5)
Scientific Reports
Scientific Reports
Resistance switching (RS) devices with ultra-thin Ta2O5 switching layer (0.5–2.0 nm) with a cell diameter of 28 nm were fabricated. The performance of the devices was tested by voltage-driven current—voltage (I-V) sweep and closed-loop pulse swit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::36b079b845e01fd19ac3bd24b907e4be
http://open-repository.kisti.re.kr/cube/handle/open_repository/486214.do
http://open-repository.kisti.re.kr/cube/handle/open_repository/486214.do
Autor:
Hyo June Kim, Hyun Min Lee, Wan Gee Kim, R. Stanley Williams, Lee Jung Hoon, Jianhua Yang, Ha Chang Jung, Beom-Yong Kim, Tae Geun Seong, Hyeong Soo Kim, Yoocharn Jeon, Jong Hee Yoo, Seonghyun Kim, Hyung Dong Lee, Kyoo Ho Jung, Seok-Hee Lee, Kee Jeung Lee, Soo Gil Kim, Suock Chung
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
In this paper, 5Xnm cross point cell array for the low power ReRAM operation was developed with 1S1R cell structure. Through the optimization of both TiOx/TaOx based-1R and NbO 2 based-1S stacks with TiN based-electrode, the world's first and best bi
Autor:
Sangsu Park, Suock Chung, Hyung Dong Lee, Seonghyun Kim, Jubong Park, Daeseok Lee, Byoung Hun Lee, Soo Gil Kim, Xinjun Liu, Seungjae Jung, Jungho Shin, Godeuni Choi, Jiyong Woo, Wootae Lee, Euijun Cha, Hyunsang Hwang, Chumhum Cho
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
We report, for the first time, the novel concept of ultrathin (∼10nm) W/NbO x /Pt device with both threshold switching (TS) and memory switching (MS) characteristics. Excellent TS characteristics of NbO 2 , such as high temperature stability (∼16
Autor:
Suock Chung, J. H. Lee, W. S. Nam, Janice H. Nickel, Hyunsang Hwang, Junkyo Suh, Kee-jeung Lee, Kwang-Ok Kim, Y. K. Kim, R.S. Williams, Yong Soo Kim, K. M. Rho, Ho-Seok Lee, Hyejung Choi, Sung Kye Park, H. S. Shin, K. Cho, J. T. Cheong, S. N. Park, S. Chae, Juyeab Lee, Kwon Hong, Sook-Joo Kim, Jianhua Yang, Seoung-Ju Chung, Seung Hwan Lee, Hyung Dong Lee, H. G. Jeong, C. G. Lee, Y. S. Sohn, Hyeon-Koo Cho, E.-R. Hwang, Frederick A. Perner, Sung-Joo Hong, Jumsoo Kim
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell are
Autor:
Jungho Shin, Jubong Park, Godeuni Choi, Jiyong Woo, Wootae Lee, Hyunsang Hwang, Hyung Dong Lee, Daeseok Lee, Soo Gil Kim, Suock Chung, Seonghyun Kim, Euijun Cha, Seungjae Jung, Sangsu Park
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
We demonstrate a varistor-type bidirectional switch (VBS) with excellent selection property for future 3D bipolar resistive memory array. A highly non-linear VBS showed superior performances including high current density (>3×107A/cm2) and high sele
Autor:
Y.-H. Seo, Sung-Woong Chung, G.-J. Park, J.-S. Rho, Hyun Mi Hwang, Adrian E. Ong, Ju-Rak Kim, Jung-Lae Park, Mun-Haeng Lee, Suk-Chul Kim, D.-H. Jung, K.-M. Rho, Vladimir Nikitin, Sung-Hyuk Cho, J.-G. Jeong, Sung-Hyung Park, Juyeab Lee, Suock Chung, H.-J. Suh, X. Tang, Dojin Kim, Y.-B. An, A. Driskill-Smith, Yong-ki Kim, Sang-Min Hwang, Jaeyun Yi, Sung-Buk Lee, Hong-Gi Kim, S. J. Hong, Gyu-An Jin
Publikováno v:
2010 International Electron Devices Meeting.
A compact STT(Spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were charac
Autor:
Suock Chung, Seonghyun Kim, Sangsu Park, Jubong Park, Min-Chul Sung, Musarrat Hasan, Joonmyoung Lee, Yu-Jun Lee, Minseok Jo, Wootae Lee, Hyejung Choi, Dong-jun Seong, D. Kil, S. J. Hong, Seungjae Jung, Nodo Lee, Yun-Taek Hwang, Jae-Sung Roh, Yun Hee Jang, Hyunsang Hwang
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
An in-depth study on the resistive switching mechanism of perovskite oxide based device was performed. Compared with filament type resistive switching device, excellent switching uniformity was obtained due to controlled redox reaction at metal/oxide
Autor:
Jai-Bum Suh, Jinwoong Kim, Se-Aug Jang, Suock Chung, Heung-Jae Cho, Jae-Geun Oh, Kwan-Yong Lim, Yong Soo Kim, Hong-Seon Yang, Soo-Young Park, Hyun-Chul Sohn, Jun-Mo Yang
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
A novel method for forming the SiO/sub 2//Si/sub 3/N/sub 4/ (O/N) gate spacer has been developed through applying a low temperature atomic layer deposition (ALD) SiO/sub 2/ film. Using this scheme, the Si-O rich interfacial dielectric layer formation