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Autor:
Sunsoo Byun, Matthew Hogan, Dina Medhat, Sherif Hany, Sunmi Choi, Jonathan James Muirhead, Mohamed ElRefaee, Jaehyun Jang, Hossam Sarhan, Baekryong Jeong, Hyunseung Choi
Publikováno v:
2020 IEEE International Integrated Reliability Workshop (IIRW).
The demand for both non-volatile (NAND) and volatile dynamic random access memory (DRAM) chips in processor and application-specific integrated circuit (ASIC) designs has grown tremendously in recent years, due largely to rapid advances in semiconduc