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pro vyhledávání: '"Sunmean Kim"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 70:766-770
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:2947-2951
We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and $2 \times 2$ ternary multipliers with various accuracies are proposed using the low-power
Autor:
Yongsu Lee, Sunmean Kim, Ho-In Lee, Seung-Mo Kim, So-Young Kim, Kiyung Kim, Heejin Kwon, Hae-Won Lee, Hyeon Jun Hwang, Seokhyeong Kang, Byoung Hun Lee
Publikováno v:
ACS nano. 16(7)
Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼10
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:3138-3151
We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit
Publikováno v:
2021 18th International SoC Design Conference (ISOCC).
Publikováno v:
2021 18th International SoC Design Conference (ISOCC).
Autor:
Jee Ho Park, Young Choi, Seong-Jin Kim, Jiwon Chang, Sunhae Shin, Kyung Rok Kim, Kyuho Jason Lee, Sunmean Kim, Woo Seok Kim, Jae Won Jeong
Publikováno v:
Nature Electronics. 2:307-312
The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make
Publikováno v:
ISCAS
This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89μΑ to 1.46μΑ
In this paper, we introduce the design and verification frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-leve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::742f332c90245e6e88554200b0e7dd10
Autor:
Sunmean Kim, Daeyeon Kim, Seokhyeong Kang, Byoung Hun Lee, Soyoung Kim, Yongsu Lee, Kiyung Kim
Publikováno v:
ISMVL
Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect p