Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Sunit Tyagi"'
Autor:
Xiaoling Wang, Patrick H. Keys, Reaz Shaheed, Obradovic Borna J, Kaizad Mistry, Stephen M. Cea, Roza Kotlyar, Cory E. Weber, Martin D. Giles, Tahir Ghani, Lucian Shifren, Sunit Tyagi, M. Stettler, Philippe Matagne
Publikováno v:
ECS Transactions. 3:429-438
Due to the success of using strain for performance gain in advanced logic technologies, strain engineering has become an important part of advanced transistor design. This paper presents process and device models that are used to provide understandin
Autor:
Kevin Zhang, Stephen H. Tang, Nagib Hakim, Gerhard Schrom, Tom Linton, Vivek De, Ali Keshavarzi, Sean Ma, Keith Bowman, Sunit Tyagi, J.R. Brews, Steven G. Duvall
Publikováno v:
ISLPED
Fluctuations in intrinsic linear V/sub T/, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic /spl rho/V/sub T/, free of extrinsic process, length and width
Autor:
M. Stettler, Scott E. Thompson, J. Xu, L. Rumaner, C. Kenyon, Robert M. Bigwood, R. Schweinfurth, B. Crew, P. Jacob, Z. Ma, W. Chen, B. McIntyre, Simon Yang, Mohsen Alavi, J. Brandenburg, Makarem A. Hussein, B. Tufts, T. Bramblett, Peter K. Moon, Sunit Tyagi, M. Bohr, C. Lo, P. Nguyen, Swaminathan Sivakumar
Publikováno v:
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//
Autor:
Stephen cea, Tahir Ghani, Martin Giles, Roza Kotlyar, Philippe Matagne, Kaizad Mistry, Borna Obradovic, Reaz Shaheed, Lucian Shifren, Mark Stettler, Sunit Tyagi, Xiaoling Wang, Cory Weber
Publikováno v:
ECS Meeting Abstracts. :1447-1447
not Available.
Conference
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