Zobrazeno 1 - 10
of 47
pro vyhledávání: '"Sunil Wickramanayaka"'
Publikováno v:
Journal of Electronic Materials. 44:2387-2395
The high-temperature requirement of Al-Ge eutectic bonding stands as a major obstacle to its wider acceptance for hermetic sealing application in the microelectromechanical systems packaging industry, in particular for temperature-sensitive devices.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d891d40a30001b337e3be2408f2f1b5
https://doi.org/10.1007/s11664-015-3683-y
https://doi.org/10.1007/s11664-015-3683-y
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
In this study, we demonstrated a TSV wafer with hybrid via with fine pitch of 6 μm and 9 μm. An effective finite element analysis (FEA) modeling methodology was developed for warpage and stress analysis by considering both silicon and Cu via effect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::091840f14fff72bc6fe66470b2ec44cd
https://doi.org/10.1109/eptc.2017.8277543
https://doi.org/10.1109/eptc.2017.8277543
Autor:
Jun Yu, Huamao Lin, King Jien Chui, Annamalai Arasu Muthukumaraswamy, Wei Yi Lim, Sunil Wickramanayaka, Leong Yew Wing, Serine Soh
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
This paper presents the design considerations for thin-film magnetic power inductors for integrated voltage regulator (IVR). Optimum design parameters for solenoid inductors are arrived at that maximize key performance metrics such as quality factor,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d859bc9cec484105b97da9344381e953
https://doi.org/10.1109/ectc.2017.289
https://doi.org/10.1109/ectc.2017.289
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddd647dbcdabdadb7897aaf2f64411ca
https://doi.org/10.1109/ectc.2017.260
https://doi.org/10.1109/ectc.2017.260
Development of wafer level laminated magnetic thin film for integrated voltage regulator application
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
In this paper we have demonstrated the 12 inch (300 mm) wafer level fabrication and characterization of a laminated CoZrTa-based magnetic thin film stack with excellent magnetic and electrical properties. Clear magnetic anisotropy with low coercivity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::481590cee593c2687ac1937a858163ae
https://doi.org/10.1109/eptc.2016.7861562
https://doi.org/10.1109/eptc.2016.7861562
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
In this study, it is shown that temporary tacking (without flux and temporary tack materials) is feasible to temporary tack Cu/SnAg or SnAg sealing ring onto Cu sealing ring at the bottom wafer. The temporary tacked samples were reflowed in a formic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d9c3da790831eb9384b291cc9cce332
https://doi.org/10.1109/eptc.2016.7861438
https://doi.org/10.1109/eptc.2016.7861438
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
Ultra-fine pitch (6μm) interconnects are essential for high-end application-products that demands high speed and high bandwidth inter-chip communication. Achieving Cu-Cu bonding with such a fine pitch is challenging since bond time is too long and b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5eab4e6e78501cf5762528c41adcce74
https://doi.org/10.1109/eptc.2016.7861452
https://doi.org/10.1109/eptc.2016.7861452
Publikováno v:
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Present study focuses on various thin wafer handling issues associated with via-last TSV fabrication integration schemes. Thin wafer handling methodology play very key role in any successful TSV interposer fabrication. Zonebond TBDB method is selecte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad37b432dae39d39e6b5a8558b0448e4
https://doi.org/10.1109/ipfa.2016.7564305
https://doi.org/10.1109/ipfa.2016.7564305
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3a8d5c0da7aafe358d41a1ea81c6811
https://doi.org/10.1109/ectc.2016.141
https://doi.org/10.1109/ectc.2016.141
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Throughput issue is limiting the adoption of 3D IC stacking process although 3D IC has many advantages in shorter communication lines, lower electrical parasitic and lower package footprint. Local thermal compression bond on each chip stack incurs en
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a149ead63a40ac968d340f3c55393c89
https://doi.org/10.1109/ectc.2016.343
https://doi.org/10.1109/ectc.2016.343