Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Sunil V. Hattangady"'
Publikováno v:
ACM Transactions on Embedded Computing Systems. 3:461-491
Many modern electronic systems---including personal computers, PDAs, cell phones, network routers, smart cards, and networked sensors to name a few---need to access, store, manipulate, or communicate sensitive information, making security a serious c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::158c2a8b6f6bb476f324cd1ed66f01cc
https://doi.org/10.1145/1015047.1015049
https://doi.org/10.1145/1015047.1015049
Autor:
Mark S. Rodder, Sunil V. Hattangady, P. Chen, Robert M. Wallace, Douglas T. Grider, P.E. Nicollian
Publikováno v:
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).
Stress-induced-leakage-current (SILC) is an important concern in ultrathin gate oxides because it may impose constraints on dielectric thickness scaling. We show that for oxides less than /spl sim/3.5 nm thick, interfacial traps generated from direct
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc63474f37f901e5fe18fd3dc3124320
https://doi.org/10.1109/relphy.1999.761646
https://doi.org/10.1109/relphy.1999.761646
Publikováno v:
Ambient Intelligence: Impact on Embedded Sytem Design ISBN: 9781402076688
Realizing the visions of ubiquitous computing and communications, and ambient intelligence will require modern electronic and computing systems to pervade all aspects of our everyday lives. These systems are used to capture, manipulate, store and com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a783d964eab8e52ca275e148140e579
https://doi.org/10.1007/0-306-48706-3_7
https://doi.org/10.1007/0-306-48706-3_7
Autor:
Monte A. Douglas, Sunil V. Hattangady, George A. Brown, P.E. Nicollian, P.A. Tiner, M. F. Pas, Robert Kraft, Douglas T. Grider, John Kuehne
Publikováno v:
International Electron Devices Meeting. Technical Digest.
A simple and novel scheme is presented for the formation of /spl sim/4 nm gate dielectric films with nitrogen at the top (gate electrode/dielectric) interface. It consists of low-temperature, remote, high-density N/sub 2/-plasma nitridation of therma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22d09b5f2778d15d1af978377ef4d693
https://doi.org/10.1109/iedm.1996.553846
https://doi.org/10.1109/iedm.1996.553846
Autor:
K. Brennan, Richard A. Chapman, M. Aoki, H.-L. Tsai, George A. Brown, Antonio L. P. Rotondaro, S.J. Fang, Amitava Chatterjee, Sunil V. Hattangady, Keith A. Joyner, H. Yang, M. Terry, G. Wilk, Robert Kraft, S. Aur, M. J. Bevan, D. Rogers, J.C. Hu, Q. He, M. Otobe, P.J. Jones, Mark S. Rodder, Ih-Chin Chen
Publikováno v:
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90c183f33b41e8aef558a93b73aa30f2
https://doi.org/10.1109/iedm.1998.746471
https://doi.org/10.1109/iedm.1998.746471
Autor:
Ih-Chin Chen, Richard A. Chapman, P.J. Chen, Sunil V. Hattangady, H.-L. Tsai, Jiong-Ping Lu, L.K. Magel, George A. Brown, Antonio L. P. Rotondaro, J.C. Hu, H. Yang, J.D. Luttmer, B. Amirhekmat, Robert Kraft
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
CVD W/CVD TiN stacks are studied for the first time as gate electrodes on 3 nm gate oxide and compared with the CVD W/PVD (sputtering) TiN gate stacks and the baseline n/sup +/ poly gate. It is found that the PVD TiN has higher metal-to-SiO/sub 2/ ba
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2353e97d0eb39a38bbc1a2ea208ce47c
https://doi.org/10.1109/iedm.1997.650423
https://doi.org/10.1109/iedm.1997.650423
Autor:
S. Murtaza, Richard A. Chapman, G. Wells, Amitava Chatterjee, R. Aggarwal, Girish A. Dixit, Wei William Lee, A. Konecni, S.J. Fang, U. Erdogan, M. Terry, George A. Brown, D. Frystak, Antonio L. P. Rotondaro, H. Yang, Robert Kraft, D. Rogers, John Kuehne, Sunil V. Hattangady, Mark S. Rodder, Q. He, Ih-Chin Chen, Chenjing Lucille Fernando, J.C. Hu, C. Bowen, M. Hanratty
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100 nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8fdef19e6d645aa123186df5fda0c6a7
https://doi.org/10.1109/iedm.1997.650507
https://doi.org/10.1109/iedm.1997.650507
Autor:
K. Brennan, Sunil V. Hattangady, S. Ashok, Mark S. Rodder, Srikanth Krishnan, S. Rangan, G. Xing
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
We have devised a novel antenna structure that distinguishes the regimes of charging during an etch process. Using this technique, we show instances in an Inductively Coupled Plasma (ICP) metal etch where charging occurs exclusively during metal clea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a09722780df428b3663492c9dc96ec6
https://doi.org/10.1109/iedm.1997.650420
https://doi.org/10.1109/iedm.1997.650420
Autor:
Richard A. Chapman, Wei William Lee, M. Hanratty, Antonio L. P. Rotondaro, Mark S. Rodder, Ih-Chin Chen, Sunil V. Hattangady, J.C. Hu, Robert Kraft, Chih-Ping Chao, H. Yang, Amitava Chatterjee
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (/spl les/33 /spl Aring/) and with high temperature (>950/spl deg/C) S/D annealing for 0.13 /spl mu/m CMOS applications. Close to ideal C-V characteristics are obtai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca93296654543f936719e26e9eb31a39
https://doi.org/10.1109/iedm.1997.650508
https://doi.org/10.1109/iedm.1997.650508
Autor:
S. Aur, Mark S. Rodder, Ih-Chin Chen, D. Rogers, Sunil V. Hattangady, J.C. Hu, Ajith Amerasekera, S. Murtaza, Chih-Ping Chao, M. Hanratty, T. Laaksonen
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
High performance 0.1 /spl mu/m (physical) gate length CMOS with 30 /spl Aring/ gate dielectric (C-V: gate accumulated at V/sub gb/=-3 V) is demonstrated at 1.0 V-1.5 V. Scaling to 0.1 /spl mu/m L/sub gate/ CMOS is described. At 1.5 V, nMOS strong and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db5ac99156f3ce4dc118cd1c6a7d7bde
https://doi.org/10.1109/iedm.1997.650349
https://doi.org/10.1109/iedm.1997.650349