Zobrazeno 1 - 10
of 28
pro vyhledávání: '"Sungpill Choi"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:4719-4732
This paper provides a review of design approaches towards artificial intelligence (AI) System-on-Chip. AI algorithms have progressed over the past decades from perceptron-based neural network (NN) and neuro-fuzzy (NF) system to today’s deep neural
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46a607f39cd731e03db520265d5aa172
https://doi.org/10.1109/tcsi.2020.2996625
https://doi.org/10.1109/tcsi.2020.2996625
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:3471-3483
An energy-efficient convolutional neural network (CNN) processor is proposed for real-time image segmentation on mobile devices. The proposed processor utilizes Region of Interest (ROI) based image segmentation to speed up the process and reduce the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7239bfa0393ba56d383158ab7ed66ab4
https://doi.org/10.1109/tcsi.2020.2991189
https://doi.org/10.1109/tcsi.2020.2991189
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 20:255-270
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab594c2d0614f338f069aa97903e1c1a
https://doi.org/10.5573/jsts.2020.20.3.255
https://doi.org/10.5573/jsts.2020.20.3.255
Publikováno v:
IEEE Solid-State Circuits Letters. 2:228-231
In this letter, we propose a low power deep reinforcement learning (DRL) SoC, supporting CNN and learning-optimized RNN, and fully connected layer. The adaptive reuse of weights and inputs, and data encoding/decoding techniques reduces power consumpt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0513678775cd1165a39260f92002ec5b
https://doi.org/10.1109/lssc.2019.2941252
https://doi.org/10.1109/lssc.2019.2941252
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 19:116-123
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::080727a603c332c4fb74f02292477a25
https://doi.org/10.5573/jsts.2019.19.1.116
https://doi.org/10.5573/jsts.2019.19.1.116
Publikováno v:
VLSI Circuits
This paper presents the first sub-10μW, sub-0.1% THD sinusoidal current generator (CG) IC that is capable of 20kHz output for the bio-impedance (Bio-Z) sensing applications. To benefit from the ultra-low-power nature of near-threshold operation, a 9
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e5e9db2f96545bcc9f1c0d0baf25194
https://doi.org/10.1109/vlsicircuits18222.2020.9162983
https://doi.org/10.1109/vlsicircuits18222.2020.9162983
Publikováno v:
VLSI Circuits
A 3D point-cloud-based neural network (PNN) processor is proposed for the low-latency hand pose estimation (HPE) system. The processor adopts the heterogeneous core architecture to accelerate both convolution layers (CLs) and sampling-grouping layers
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52fbaad4f142d46d215ec1771632d0dd
https://doi.org/10.1109/vlsicircuits18222.2020.9162895
https://doi.org/10.1109/vlsicircuits18222.2020.9162895
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:115-123
A Low-power convolutional neural network (CNN)-based face recognition system is proposed for the user authentication in smart devices. The system consists of two chips: an always-on CMOS image sensor (CIS)-based face detector (FD) and a low-power CNN
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7da2fe95971478872ddc2712ceb3e8a4
https://doi.org/10.1109/jssc.2017.2767705
https://doi.org/10.1109/jssc.2017.2767705
Publikováno v:
IEEE Micro. 37:30-38
The authors propose a low-power convolutional neural network (CNN)-based face recognition system for user authentication in smart devices. The system comprises two chips: an always-on functional CMOS image sensor (CIS) for imaging and face detection
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4d8784f20c8304cc822c72442f7e2e7
https://doi.org/10.1109/mm.2017.4241350
https://doi.org/10.1109/mm.2017.4241350
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 63:2180-2188
A low-latency and low-power stereo matching accelerator is monolithically integrated with a CMOS image sensor (CIS) for mobile applications. To reduce the overall latency, focal-plane processing is adopted by using the proposed analog census transfor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f6968aa5f8bac2284ce1495a207a6d9
https://doi.org/10.1109/tcsi.2016.2619718
https://doi.org/10.1109/tcsi.2016.2619718