Zobrazeno 1 - 10
of 51
pro vyhledávání: '"Sungjun Chun"'
Autor:
Pavel Roy Paladhi, Yanyan Zhang, Xianbo Yang, Nam Pham, Megan Nguyen, Mahesh Bohra, Junyan Tang, Sungjun Chun, Joshua Myers, Wiren Becker, Daniel Dreps
Publikováno v:
2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d47ccc8d7f016a55b6ff64cb7d12e00
https://doi.org/10.1109/epeps53828.2022.9947103
https://doi.org/10.1109/epeps53828.2022.9947103
Autor:
Wiren D. Becker, Daniel M. Dreps, Pavel Roy Paladhi, Brian Samuel Beaman, Yanyan Zhang, Jose A. Hejase, Junyan Tang, Daniel Rodriguez, Sungjun Chun
Publikováno v:
2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
A comprehensive signal integrity model to hardware correlation study on an improved, 44 Gb/s capable, hybrid land grid array (HLGA) socket connector design is presented. The connector only design SI performance is shown through 3D electromagnetic (EM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18caab087dcff7de491f99354276ba92
https://doi.org/10.1109/epeps48591.2020.9231393
https://doi.org/10.1109/epeps48591.2020.9231393
Autor:
Megan Nguyen, Brian Samuel Beaman, Dale Becker, Kevin M. McIlvain, Zhineng Fan, Junyan Tang, Biao Car, Abhijit Wander, Glen A. Wiedemeier, Hongqing Zhang, Sungjun Chun, Daniel M. Dreps, Brian J. Connolly, Zhaoqin Chen, Yifan Huang, Jose A. Hejase, Victor Mahran, Kyle Giesen, Baughen Devon
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
DDR5 Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate per data differential pair being specified at 25.6Gb/s minimum at present and at 51.2Gb/s maximum in the future. This is a significa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e9136c15f300b3bc939a6c76c3ccc5b
https://doi.org/10.1109/ectc32862.2020.00158
https://doi.org/10.1109/ectc32862.2020.00158
Autor:
Yanyan Zhang, Pavel Roy Paladhi, Sungjun Chun, Lei Shan, Jose A. Hejase, Jean Audet, Mahesh Bohra, Wiren D. Becker, Daniel M. Dreps
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
A novel edge card connector design approach with tunable signal integrity (SI) properties is proposed. The tunability is achieved through the presence or absence of a grounded conductive fixture in between the connector pin rows. The main purpose of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64736c919272eb2e598c24d0968f5c23
https://doi.org/10.1109/epeps47316.2019.193238
https://doi.org/10.1109/epeps47316.2019.193238
Autor:
Joshua C. Myers, Daniel M. Dreps, Prasanna Jayaraman, Wiren D. Becker, Junyan Tang, Pavel Roy Paladhi, Yanyan Zhang, Nam H. Pham, Sungjun Chun, Jose A. Hejase
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
While equalization is usually a positively contributing factor towards opening eye diagrams further, sometimes over equalization can occur and degrade an eye opening as opposed to improve it. This paper explores the effectiveness of using post-cursor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e59a3349a92dbdbd36ef876f514eda04
https://doi.org/10.1109/epeps47316.2019.193221
https://doi.org/10.1109/epeps47316.2019.193221
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
Effects of PCB wiring in tightly pitched module pin fields on high speed channel signal integrity are evaluated in this paper. Three different module orthogonal pin pitches are considered: 0.8mm, 1.06mm and 1.27mm. Each of the pin pitch scenarios is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce96992efe438aa5b216ec45d1cd1637
https://doi.org/10.1109/epeps47316.2019.193216
https://doi.org/10.1109/epeps47316.2019.193216
Autor:
Daniel M. Dreps, Wiren D. Becker, Sungjun Chun, Joshua C. Myers, Pavel Roy Paladhi, Jose A. Hejase, Junyan Tang
Publikováno v:
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
In this paper, transitions between substrate integrated waveguides (SIW) within a multi-layered printed circuit board (PCB) are studied. Particularly, horizontal (within the same layer) and vertical (between different layers) transitions are investig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a815518e3d99567abecbfd38d3807fb9
https://doi.org/10.1109/epeps.2018.8534285
https://doi.org/10.1109/epeps.2018.8534285
Autor:
Pavel RoyPaladhi, Dale Becker, Sungjun Chun, Junyan Tang, Joshua C. Myers, Daniel M. Dreps, Jose A. Hejase
Publikováno v:
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
This paper explores a new passive coupling technique for multi-band high speed signaling in Substrate Integrated Waveguides (SIW). Two monopole antenna feeds operating at two different center frequencies are used for coupling signals into the SIW. Mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe15f0b93816c285ade090715ec781f9
https://doi.org/10.1109/epeps.2018.8534265
https://doi.org/10.1109/epeps.2018.8534265
Publikováno v:
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
This paper presents an improved hybrid land grid array socket connector design enabling high speed bus signaling data rates up to 50Gb/s. Observed limitations in an existing connector such as impedance mismatches and crosstalk are treated and improve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ba8387431a97d41495100b763af29b9
https://doi.org/10.1109/epeps.2017.8329761
https://doi.org/10.1109/epeps.2017.8329761
Autor:
Glen A. Wiedemeier, Lloyd A. Walls, Jose A. Hejase, Francesco Preda, Jean Audet, Daniel Douriet, Dale Becker, Junyan Tang, Sungjun Chun, Megan Nguyen, Daniel M. Dreps
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
A 19.2 Gb/s per lane link with IBM's latest POWER8 processor module has been analyzed. This paper presents the overview of the high-speed link design from the signal integrity point of view. Design approaches in package and printed circuit board (PCB
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d46f3165dba67c5ec9f8673302c69a9
https://doi.org/10.1109/ectc.2017.170
https://doi.org/10.1109/ectc.2017.170