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pro vyhledávání: '"Sung-Sop Lee"'
Publikováno v:
ISCAS (3)
In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4/spl times/ oversampling phase detector (PD) structure is described. The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf7b86c72cbdbe54c45f72210c7e0aed
https://doi.org/10.1109/iscas.2005.1465056
https://doi.org/10.1109/iscas.2005.1465056
Publikováno v:
Proceedings 2005 IEEE International SOC Conference; 2005, p11-14, 4p
Publikováno v:
2005 IEEE International Symposium on Circuits & Systems; 2005, p2192-2192, 1p