Zobrazeno 1 - 10
of 571
pro vyhledávání: '"Sung-Kyu Lim"'
Publikováno v:
Micromachines, Vol 12, Iss 1, p 89 (2021)
This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO2 layer as an InP etch mask and conventional inductively coup
Externí odkaz:
https://doaj.org/article/721d903c64cb41668e61ff9146767d0e
Autor:
Michael Hoffmann, Zheng Wang, Nujhat Tasneem, Ahmad Zubair, Prasanna Venkatesan Ravindran, Mengkun Tian, Anthony Arthur Gaskell, Dina Triyoso, Steven Consiglio, Kandabara Tapily, Robert Clark, Jae Hur, Sai Surya Kiran Pentapati, Sung Kyu Lim, Milan Dopita, Shimeng Yu, Winston Chern, Josh Kacher, Sebastian E. Reyes-Lillo, Dimitri Antoniadis, Jayakanth Ravichandran, Stefan Slesazeck, Thomas Mikolajick, Asif Islam Khan
Publikováno v:
Nature Communications, Vol 13, Iss 1, Pp 1-8 (2022)
Applying an electric field to an antiferroelectric material transforms its non-polar crystal structure into a polar one. Here, the authors show that the antiferroelectric transition in zirconia causes a negative capacitance, useful for electronics.
Externí odkaz:
https://doaj.org/article/a3714ccb4ef949fda04b550a059cfdef
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 7, Iss 1, Pp 26-34 (2021)
In a 2-D design, the block pins are located at the periphery of a block optimally since blocks are placed side-by-side horizontally in a single placement layer. However, monolithic 3-D (M3D) integration relieves this boundary constraint by allowing v
Externí odkaz:
https://doaj.org/article/8c4123e96c08456c8d1ab32441e1ddd5
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 7, Iss 2, Pp 106-114 (2021)
This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and
Externí odkaz:
https://doaj.org/article/df1b2c62224146cda435cc567414f305
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 28:1-22
Modern electronic design automation flows depend on both implementation and signoff tools to perform timing-constrained power optimization through Engineering Change Orders (ECOs), which involve gate sizing and threshold-voltage ( V th )-assignment o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06885b2fa57cde93f7144a9e2b94c28a
https://doi.org/10.1145/3569942
https://doi.org/10.1145/3569942
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42:1295-1308
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f16d5ef2adffe38683dedfadb5b501c5
https://doi.org/10.1109/tcad.2022.3193647
https://doi.org/10.1109/tcad.2022.3193647
Autor:
Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto Garcia-Ortiz, Dragomir Milojevic, Francky Catthoor, Gioele Mirabelli, Manu Komalan, Sung Kyu Lim
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 13:300-314
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3700b111b83615863f35135f8e2f25e1
https://doi.org/10.1109/tcpmt.2023.3264520
https://doi.org/10.1109/tcpmt.2023.3264520
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31:296-309
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9058e7c86340422c43d38fa1b748805
https://doi.org/10.1109/tvlsi.2022.3228850
https://doi.org/10.1109/tvlsi.2022.3228850
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 12:1969-1982
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::353fae515bf114ac07581f387044399f
https://doi.org/10.1109/tcpmt.2022.3221025
https://doi.org/10.1109/tcpmt.2022.3221025
Publikováno v:
Applied Sciences, Vol 11, Iss 24, p 12151 (2021)
We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3D
Externí odkaz:
https://doaj.org/article/a4aecb52b7544b99ae2597dae0977606