Zobrazeno 1 - 10
of 106
pro vyhledávání: '"Sung Kye Park"'
Publikováno v:
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
Publikováno v:
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
Autor:
Hyoungcheol Kwon, Felipe Iza, Imhee Won, Minkyung Lee, Songhee Han, Raseong Park, Yongjin Kim, Dongyean Oh, Sung-Kye Park, Seonyong Cha
Publikováno v:
Physics of Plasmas. 30:013504
The formation of high-energy electrons and ion fluxes induced by an abnormal electron heating mode in asynchronous pulse-modulated plasma was investigated using particle-in-cell simulation. We demonstrate that the abnormally high electron heating mod
Autor:
Hyoungcheol Kwon, Imhee Won, Songhee Han, Dong-Hun Yu, Deuk-Chul Kwon, Yeon Ho Im, Felipe Iza, Dongyean Oh, Sung-Kye Park, Seonyong Cha
Publikováno v:
Physics of Plasmas. 29:093510
Vertical scaling technique faces a physical limitation in 3D NAND device fabrication, even assuming superior etching technology. Another promising scaling technique to increase the storage density is lateral scaling, which increases the number of hol
Autor:
Hyoungcheol Kwon, Hyunsuk Huh, Hwiwon Seo, Songhee Han, Imhee Won, Jiwoong Sue, Dongyean Oh, Felipe Iza, Seungchul Lee, Sung Kye Park, Seonyong Cha
Publikováno v:
Physics of Plasmas. 29:073504
Cost-effective vertical etching of plug holes and word lines is crucial in enhancing 3D NAND device manufacturability. Even though multiscale technology computer-aided design (TCAD) methodology is suitable for effectively predicting etching processes
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
We have fabricated a recessed gate (RG) transistor for sense amplifier (SA) in high density DRAM and have compared it with a conventional planar gate (PG) transistor in terms of VT mismatch performance. The mismatch was reduced into 22% compared to P
Autor:
Byungin Lee, Hyun-Seung Yoo, Sung-Kye Park, Yong Jun Kim, Gyu-Seog Cho, Hyug Su Kwon, Woo Young Choi, SangMoo Choi
Publikováno v:
IEEE Electron Device Letters. 38:164-167
The influence of intercell trapped charge (ITC)-the charge trapped at the inter-cell nitride regions by fringe electric fields during program and erase operations-on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degr
Autor:
Daewoong Kwon, Joo Yun Seo, Byung-Gook Park, Sang-Ho Lee, Sung-Kye Park, Gyu Seong Cho, Wandong Kim, Se Hwan Park, Do-Bin Kim
Publikováno v:
IEEE Electron Device Letters. 37:1418-1421
In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed st
Autor:
Jong-Ho Lee, Do-Bin Kim, Eun-Seok Choi, Gyu Seog Cho, Sung-Kye Park, Joo Yun Seo, Sang-Ho Lee, Byung-Gook Park, Wandong Kim, Daewoong Kwon
Publikováno v:
IEEE Transactions on Electron Devices. 63:3521-3526
In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage ( $V_{\mathrm{ th}}$ ) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs
Autor:
Jong-Ho Lee, Sang-Ho Lee, Wandong Kim, Daewoong Kwon, Gyu Seong Cho, Do-Bin Kim, Eun-Seok Choi, Ji-Ho Park, Joo Yun Seo, Sung-Kye Park, Myung-Hyun Baek, Byung-Gook Park
Publikováno v:
IEEE Transactions on Electron Devices. 63:1041-1046
Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages ( $V_{\textrm {th}}$ ) of string select transistors (SSTs)/dummy SSTs. There are additional unsele