Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Sunfei Fang"'
Autor:
E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao
Publikováno v:
2014 IEEE International Electron Devices Meeting.
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat
Autor:
Rajeev Malik, Rishikesh Krishnan, Sunfei Fang, Bernhard Wunder, Kevin McStay, Yanli Zhang, Sadanand V. Deshpande, Douglas Daley, Herbert L. Ho, Sneha Gupta, Paul C. Parries, Balaji Jayaraman, Sungjae Lee, Puneet Goyal, John E. Barth, Scott R. Stiffler, Paul D. Agnello, Subramanian S. Iyer
Publikováno v:
ICICDT
In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap)
Autor:
Herbert L. Ho, Jinping Liu, Paul C. Parries, Norman Robson, Jing Li, Puneet Goyal, S.S. Iyer, Ming Yin, Babar A. Khan, Zhengwen Li, Paul D. Agnello, K. V. Hawkins, Sunfei Fang, T. Weaver, Scott R. Stiffler, Kevin McStay, Rishikesh Krishnan, W. Davies, R. Takalkar, T. Kirihata, Sami Rosenblatt, S. Galis, A. Blauberg, Shreesh Narasimha, Michael P. Chudzik, Amanda L. Tessier, William K. Henson, W. Kong, Edward P. Maciejewski, Alberto Cestero, Nauman Zafar Butt, Joseph Ervin, S. Gupta, Jeyaraj Antony Johnson, S. Rombawa, Sungjae Lee, J. Barth, Ying Zhang
Publikováno v:
2010 International Electron Devices Meeting.
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovat
Autor:
Russell H. Arndt, Ashima B. Chakravarti, Anthony G. Domenicucci, Amanda L. Tessier, Jinping Liu, Sunfei Fang, Kevin McStay, Zhengwen Li, Randolph F. Knarr, S. Lee, Joseph F. Shepard, Herbert L. Ho, A. Arya, R. Venigalla, W. Davies, R. Takalkar, Rishikesh Krishnan, Paul C. Parries, B. Morgenfeld, Xin Li, S. Gupta, Michael P. Chudzik, Scott R. Stiffler, Puneet Goyal, Babar A. Khan, Sadanand V. Deshpande, J. Dadson, Scott D. Allen
Publikováno v:
2010 IEEE International SOI Conference (SOI).
In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has
Autor:
S.S. Iyer, Ravi M. Todi, Rajeev Malik, Erik A. Nelson, Rishikesh Krishnan, Sunfei Fang, Byeong Y. Kim, R. Takalkar, D. Anand, Oh-Jung Kwon, Michael P. Chudzik, Nauman Zafar Butt, Scott R. Stiffler, Herbert L. Ho, Joseph Ervin, Siddarth A. Krishnan, Babar A. Khan, Alberto Cestero, Gregory G. Freeman, Geng Wang, Karen A. Nummy, J. Sim, Amanda L. Tessier, Jin Liu, W. Kong, Paul C. Parries, Kevin McStay
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRA
Autor:
A. Mallikarjunan, Hosadurga Shobha, Xinlin Wang, Ghavam G. Shahidi, Chun-Yung Sung, Eric A. Joseph, Sunfei Fang, Isaac Lauer, Eva E. Simonyi, Sampath Purushothaman, Wilfried Haensch, Nicholas C. M. Fuller, C. Ouyang, Tien Cheng, Huiming Bu, Elbert E. Huang
Publikováno v:
2008 IEEE International SOI Conference.
Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overl
Autor:
Ying Li, Sadanand V. Deshpande, J. Yuan, R. Divakaruni, Oleg Gluschenkov, Heon Lee, V. Sardesai, Victor Chan, Sunfei Fang, Y.T. Chow, T. Kebede, Carl J. Radens, N. Cave, C. Ryou, S.S. Naragad, Roger A. Booth, W. Wille, Manfred Eller, Helen Wang, JiYeon Ku, J.H. Yang, Nivo Rovedo, O.S. Kwon, H. Shang, V. Vidya, Narasimhulu Kanike, W. Clark, C.W. Lai, J. Yan, J. Liang, M.R. Visokay, J. Sudijono, H. Mo, Oh-Jung Kwon, Y. Gao
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme
Autor:
Erdem Kaltalioglu, Zhijiong Luo, Victor Ku, Y. H. Lin, A. Ajmera, Seong-Dong Kim, T. Schiml, W. L. Tan, S. Marokkey, P. Wrschka, Dirk Vietzke, M. Weybright, F.F. Jamin, R. Mo, D.-G. Park, An L. Steegen, Wenhe Lin, Padraic Shafer, Terence B. Hook, V. Klee, JiYeon Ku, Rajesh Rengarajan, C. Wann, K. Kim, Jenny Lian, Andy Cowley, Victor Chan, Sunfei Fang, A. Vayshenker, K-C. Lee, Christopher V. Baiocco, I. Yang, L. Kim, Manfred Eller, Randy W. Mann, B. Zhang, C. Coppock, Mark Hoinkis, J. Sudijono, Huilong Zhu, Phung T. Nguyen
Publikováno v:
Scopus-Elsevier
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and l
Autor:
Jinghong Li, Angela Lamberti, Anthony Domenicucci, Henry Utomo, Nivo Rovedo, Zhijiong Luo, Sunfei Fang, Hung Ng, Judson R. Holt, Anita Madan, Chung Woh Lai, Ja-Hum Ku, Dominic J. Schepis, Jin-Ping Han
Publikováno v:
ECS Meeting Abstracts. :2437-2437
not Available.
Autor:
E. Gusev, Cyril Cabral, Young-Hee Kim, Barry Linder, Eduard Cartier, Sufi Zafar, Paul Jamison, Hasan Nayfeh, Sunfei Fang
Publikováno v:
ECS Meeting Abstracts. :703-703
not Available.