Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Sundaram Ananthanarayanan"'
Autor:
Sundaram Ananthanarayanan, Balaji Varadarajan, Ali-Reza Adl-Tabatabai, Masoud Saeida Ardekani, Simon Soriano, Denis Haenikel, Dhaval H Patel
Publikováno v:
EuroSys
Giant monolithic source-code repositories are one of the fundamental pillars of the back end infrastructure in large and fast-paced software companies. The sheer volume of everyday code changes demands a reliable and efficient change management syste
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8368ebb82ac3dbb7edb979d27b077a71
https://doi.org/10.1145/3302424.3303970
https://doi.org/10.1145/3302424.3303970
Autor:
Aravindkumar Rajendiran, Mahesh V. Tripunitara, Hiren D. Patel, Siddharth Garg, Dan Wang, Sundaram Ananthanarayanan
Publikováno v:
IEEE Micro. 34:86-94
This work presents a method to reliably perform computations in the presence of both hard faults arising from aggressive technology scaling and design defects from human error. The method is based on the observation that a single Turing-complete inst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6dcda048aef265667368f9cd37976d84
https://doi.org/10.1109/mm.2013.130
https://doi.org/10.1109/mm.2013.130
Autor:
Aravindkumar Rajendiran, Siddharth Garg, Hiren D. Patel, Sundaram Ananthanarayanan, Mahesh V. Tripunitara
Publikováno v:
DAC
This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on an observation that a single Turing-complete instructi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b00e939a2a3840313540c20f0a252699
https://doi.org/10.1145/2228360.2228485
https://doi.org/10.1145/2228360.2228485
Publikováno v:
FPGA
Dynamic power management for multi-core system on chip (MPSoC) platforms has become an increasingly critical design problem. In this paper, we present EmPower, an FPGA based emulation, validation and prototyping framework for dynamic power management
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13339cd9e4d1b098967e24664630c6b2
https://doi.org/10.1145/2145694.2145744
https://doi.org/10.1145/2145694.2145744