Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Sumiko Doumae"'
Autor:
Shinichiro Shiratake, Ryu Ogiwara, Ryousuke Takizawa, Hidehiro Shiga, Sumiko Doumae, Daisaburo Takashima
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:1324-1331
This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both “1” and “0
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a36318df5606f4a8053b02f3fbddd18
https://doi.org/10.1109/jssc.2015.2405932
https://doi.org/10.1109/jssc.2015.2405932
Autor:
Shuso Fujii, Daisaburo Takashima, Ryu Ogiwara, Daisuke Hashimoto, Akihiro Nitayama, Shinichiro Shiratake, Ryo Fukuda, Susumu Shuto, Yohji Watanabe, Hidehiro Shiga, Tohru Ozaki, Katsuhiko Hoya, Iwao Kunishima, Tadashi Miyakawa, Sumiko Doumae, Takeshi Hamamoto, Hiroyuki Kanaya, Ryosuke Takizawa, Koji Yamakawa
Publikováno v:
ISSCC
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5daa454ca9ff7463fb3e94791bd14491
https://doi.org/10.1109/jssc.2011.2159053
https://doi.org/10.1109/jssc.2011.2159053
Autor:
Shinichiro Shiratake, Yoshinori Kumura, S. Ohtsuki, Hitoshi Shiga, Sumiko Doumae, Iwao Kunishima, T. Ozaki, Daisaburo Takashima, Tadashi Miyakawa, Ryu Ogiwara, Akihiro Nitayama, Koji Yamakawa, Katsuhiko Hoya, Syuso Fujii, Susumu Shuto
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1745-1752
A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a05654e47ec1032b385902092e35fa7e
https://doi.org/10.1109/tvlsi.2009.2034380
https://doi.org/10.1109/tvlsi.2009.2034380
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0
https://doi.org/10.1109/jssc.2009.2034414
https://doi.org/10.1109/jssc.2009.2034414
Autor:
Iwao Kunishima, Masahiro Kamoshida, Y. Itoh, Ryu Ogiwara, Koji Yamakawa, Yukihito Oowaki, Sumiko Doumae, Yoshiaki Takeuchi, Hiroyuki Kanaya, M. Aoki, Daisaburo Takashima, Katsuhiko Hoya, T. Ozaki, Tadashi Miyakawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1713-1720
This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-/spl mu/m 2-metal CMOS technology. A small die of 76 mm/sup 2/ and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1328823be39788f7539d6e6dfd274a0e
https://doi.org/10.1109/4.962293
https://doi.org/10.1109/4.962293
Autor:
S. Ohtsuki, S. Tanaka, H. Takenakal, Ryu Ogiwara, O. Hidaka, Sumiko Doumae, Y. Itoh, Susumu Shuto, Tadashi Miyakawa, Yoshiaki Takeuchi, Iwao Kunishima
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:545-551
A 0.5-/spl mu/m, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e2bb6e8df004b1fb8ff58129be75cbf
https://doi.org/10.1109/4.839914
https://doi.org/10.1109/4.839914
Autor:
Tadashi Miyakawa, Ryu Ogiwara, Sumiko Doumae, Y. Itoh, H. Takenaka, Yoshiaki Takeuchi, S. Tanaka, H. Kamata
Publikováno v:
IEEE Transactions on Electron Devices. 47:781-788
A new ferroelectric random access memory (FRAM) cell design with high immunity to fatigue and imprint has been proposed in order to achieve a megabit class FRAM with 1T1C cell structure, and has been applied to a 1 M bit FRAM operated from a 3(V) sup
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bddce0dc4838334745caec7a971dcd58
https://doi.org/10.1109/16.830994
https://doi.org/10.1109/16.830994
Autor:
Shinichiro Shiratake, Sumiko Doumae, Ryousuke Takizawa, Hidehiro Shiga, Daisaburo Takashima, Ryu Ogiwara
Publikováno v:
2010 IEEE Asian Solid-State Circuits Conference.
This paper presents highly reliable reference bitline bias designs for 64Mb and 128Mb chain FeRAM™. In order to compensate cell signal level shift of both "1" and "0" data inherent to ferroelectric material, the band-gap reference circuit with temp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d2b200264ea9d185a97c097ab9fcfac
https://doi.org/10.1109/asscc.2010.5716634
https://doi.org/10.1109/asscc.2010.5716634
Autor:
Ryu Ogiwara, Syuso Fujii, Iwao Kunishima, Daisaburo Takashima, Yoshinori Kumura, Hitoshi Shiga, S. Ohtsuki, Akihiro Nitayama, Shinichiro Shiratake, Sumiko Doumae, Tadashi Miyakawa, T. Ozaki, Koji Yamakawa, Katsuhiko Hoya, Susumu Shuto
Publikováno v:
ISSCC
A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::584065a7f06dedbb7ebf7903987f8b3b
https://doi.org/10.1109/isscc.2006.1696078
https://doi.org/10.1109/isscc.2006.1696078