Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Sumant Sood"'
Publikováno v:
ECS Transactions. 27:801-806
Temporary bonding attaches substrates to a carrier so that after thinning to the desired thickness further backside fabrications steps can be conducted with "normal" process flows in standard semiconductor equipment. The selection of a suitable tempo
Publikováno v:
ECS Transactions. 33:17-26
Diffusion and eutectic bonding are gaining broad acceptance in 3D integration and packaging. Many bonding schemes are based on copper because this material is used extensively in FEOL, has a well developed CMP history and high yield TSV's have been p
Autor:
Jürgen Burggraf, Julian Bravin, Sina Jahanbin, Markus Wimplinger, Sumant Sood, Paul Lindner, Thomas Uhrmann, Prashant Aji, Jie Gong, Rohit Bhat
Publikováno v:
2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
As 3D-TSV technology based solutions are moving into volume manufacturing, monitoring of the processed device wafer through temporary bonding, thinning, TSV reveal, metallization and de-bonding processes remains a key yield concern. Edge chipping, mi
Autor:
Rona Belford, Sumant Sood
Publikováno v:
ECS Transactions. 3:99-106
We present various pre-bonding treatments in conjunction with co-implantation cleaving kinetics en route to producing strained silicon on quartz (SSOQ). This surface activation study presents the ground work for elevated temperature bonding required
Autor:
Alain Phommahaxay, Youssef Travaly, T. Buisson, Peter Bisson, Dan Wallace, Sumant Sood, Mark Privett, Bart Swinnen, Eric Beyne, Anne Jourdain
Publikováno v:
3DIC
Thin wafer handling has become a very challenging topic of emerging 3D technologies, and temporary wafer bonding to a carrier support wafer is one way to guarantee the required mechanical stability and rigidity to the thin wafer during subsequent bac
Publikováno v:
3DIC
While several methods are available and in production for power devices, LED or other markets, 200mm and 300mm temporary bonding for 3D integration is a quite new field for material and equipment suppliers and challenging all participants in the supp
Autor:
Jan Van Olmen, Anne Jourdain, Sumant Sood, Shari Farrens, Philippe Soussan, Alain Phommahaxay, Cedric Huyghebaert, Yann Civale
Publikováno v:
2010 IEEE International Interconnect Technology Conference.
In this paper we report on the use of Silicon wafer to wafer bonding technology using Trough Silicon Vias (TSV) and Cu to Cu hybrid interconnects. We demonstrate that multiple wiring levels of two separate wafers, can be interconnected on a full wafe
Publikováno v:
ECS Meeting Abstracts. :1718-1718
not Available.
Autor:
Shari Farrens, Sumant Sood
Publikováno v:
ECS Meeting Abstracts. :1706-1706
not Available.
Publikováno v:
ECS Meeting Abstracts. :1695-1695
There is a growing demand for MEMS wafer packaging processes where the CMOS wafer can be bonded to a MEMS wafer using CMOS foundry compatible materials. Most current MEMS packaging applications either use glass frit and anodic bonding or metals such