Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Suman Jaiswal"'
Autor:
Nurul Azam, Matthew G. Boebinger, Suman Jaiswal, Raymond R. Unocic, Parvin Fathi-Hafshejani, Masoud Mahjouri-Samani
Publikováno v:
ACS Applied Nano Materials. 5:9129-9139
Autor:
Parvin Fathi-Hafshejani, Nurul Azam, Suman Jaiswal, Lu Wang, Marcelo Kuroda, Michael C. Hamilton, Sahar Hasim, Masoud Mahjouri-Samani
Publikováno v:
Frontiers in Biological Detection: From Nanosensors to Systems XV.
Publikováno v:
Medical Engineering & Physics. 115:103973
Publikováno v:
Mechanics Research Communications. 129:104098
Publikováno v:
2D Photonic Materials and Devices V.
Publikováno v:
Journal of Statistics Applications & Probability Letters. 3:71-81
Publikováno v:
2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).
This paper investigates the failure mechanism of Ultra High Voltage JFET (UHV-JFET) under Unclamped Inductive Switching (UIS) test. We explain the ruggedness failure of the Power MOSFETs based on drain impact ionization event, diffusion current flowi
Autor:
Suman Jaiswal, S. Krishna Sai, Chirag Aryadeep, Muntha Sai Dheeraj, Gene Sheu, Chen Po-An, Shaik Mastanbasheer, Sivaji Selvendran, Syed Neyaz Imam
Publikováno v:
2017 6th International Symposium on Next Generation Electronics (ISNE).
An innovative and improved UMOSFET device with low specific on-resistance maintain desired breakdown voltage up to 100V. In this proposed device, p-pillar under the p+ region UMOS structure has been developed and successfully simulated by using 2D si
Publikováno v:
2017 6th International Symposium on Next Generation Electronics (ISNE).
Simulation tools are very important to develop process and design a new device structures. Device characteristics and physics phenomena also can be analyzed and predicted using this tools. High energy implantation of dopant atoms is used to form buri
Autor:
Chirag Aryadeep, S. Krishna Sai, Suman Jaiswal, Chen Po-An, Muntha Sai Dheeraj, Shaik Mastanbasheer, Sivaji Selvendran, Gene Sheu
Publikováno v:
2017 6th International Symposium on Next Generation Electronics (ISNE).
An innovative and improved UMOS device structure, with gate oxide 900 to 1500A, breakdown voltage 40 to 100V, robust to hot carrier injection (HCI) stress is proposed. We demonstrate and report the effect of p-type and n-type doping in gate oxide and