Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Sukalpa Biswas"'
Autor:
Sukalpa Biswas, Alex Wright
The last decade has seen a very gradual change at a local network level in the methods used to collect data from Highways Infrastructure Assets, how to manage and operate Assets, a change in the way those Assets are used, and the way they are maintai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2667c6881e7aeb7fd1af77f33ed2df9a
https://doi.org/10.58446/cwlm6036
https://doi.org/10.58446/cwlm6036
Autor:
Sukalpa Biswas, John Proust, Tadas Andriejauskas, Alex Wright, Carl Van Geem, Darko Kokot, António Antunes, Vânia Marecos, José Barateiro, Shubham Bhusari, Jelena Petrović
Publikováno v:
Sustainable Civil Infrastructures ISBN: 9783030798000
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61d4f91fe93004981397c9a0c11679ab
https://doi.org/10.1007/978-3-030-79801-7_27
https://doi.org/10.1007/978-3-030-79801-7_27
Autor:
Sukalpa Biswas, John Proust, Tadas Andriejauskas, Alex Wright, Carl van Geem, Darko Kokot, António Antunes, Vânia Marecos, José Barateiro, Shubham Bhusari, Uros Jovanovic
Publikováno v:
IOP Conference Series: Materials Science and Engineering. 1202:012002
Road infrastructure asset management is rapidly transforming into a digital environment where data accessibility, effective integration and collaboration and accessibility from different sources and assets are key. However, current asset management p
Autor:
Zongjian Chen, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Dan Murray, Eric Shiu, Priya Ananthanarayanan, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tam, Pradeep Trivedi, James Wang, Ricky Wen, John Yong, Sukalpa Biswas, Brian Campbell, Hao Chen, Shailendra Desai, Shaishav Desai, Dominic Go, Rajat Goel
Publikováno v:
ISSCC
An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design tec