Zobrazeno 1 - 10
of 72
pro vyhledávání: '"Suk-Kang Sung"'
Autor:
Suk-Kang Sung, Jai-Hyuk Song, Jeong-Hyuk Choi, Wang-Chul Shin, Jun-Eui Song, Du-Heon Song, Y. Roh, Yong-Sik Yim, Jin-Yong Ryoo
Publikováno v:
ECS Transactions. 58:69-73
This paper describes the influence of water-related species contained in intermetal dielectric layer on the interpoly dielectric properties of nonvolatile memory devices. P-TEOS layer used as an intermetal dielectric enhances degradation of interpoly
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ad484e3b7412454248b0468f0c447b12
https://doi.org/10.1149/05805.0069ecst
https://doi.org/10.1149/05805.0069ecst
Autor:
Sunghyun Kwon, Kinam Kim, Byung Yong Choi, Min Tai Yu, Tae Hun Kim, Keon-Soo Kim, Dong Hoon Jang, Min Jeong Kim, Se-Hoon Lee, Min Cheol Park, Mi So Hwang, Jung-Dal Choi, Choong-ho Lee, Suk Kang Sung, Se-Jun Park, Min-cheol Kim
Publikováno v:
Journal of the Korean Physical Society. 56:142-146
A fully calibrated 3-D simulation of a NAND flash string is used to characterize the source/drain hot carrier disturbance phenomenon for the first time. Through the word line 31 (WL31) program voltage (Vpgm) disturbances simulation with various pass
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf45a0214f82348d39afa18f6349f8b0
https://doi.org/10.3938/jkps.56.142
https://doi.org/10.3938/jkps.56.142
Publikováno v:
Journal of the Korean Physical Society. 53:1919-1922
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa607852fba34932d7da1404345c2953
https://doi.org/10.3938/jkps.53.1919
https://doi.org/10.3938/jkps.53.1919
Autor:
Dong-gun Park, Byung Yong Choi, Choong-ho Lee, Chang Woo Oh, Byung-Kyu Cho, Suk-Kang Sung, Tae-yong Kim, Eun Suk Cho, Hye-Jin Cho
Publikováno v:
IEEE Transactions On Nanotechnology. 5:174-179
Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a64a9583c37bb1930530bc34317ddf9
https://doi.org/10.1109/tnano.2006.869954
https://doi.org/10.1109/tnano.2006.869954
Autor:
Chilhee Chung, Jong Duk Lee, Byung-Gook Park, Donggun Park, Sung Taeg Kang, Jae Sung Sim, Yong Kyu Lee, Suk Kang Sung, Ki Whan Song, Kinam Kim
Publikováno v:
Solid-State Electronics. 48:1771-1775
A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e14cd72fb787a390e437a0b7f6a431f
https://doi.org/10.1016/j.sse.2004.05.048
https://doi.org/10.1016/j.sse.2004.05.048
Autor:
Soo Doo Chae, Yong Kyu Lee, Chung Woo Kim, Suk-Kang Sung, Jong Duk Lee, Chang Ju Lee, Il-han Park, Byung-Gook Park
Publikováno v:
IEEE Transactions On Nanotechnology. 2:258-264
In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9464639ab63968a287b1d0de94c19b40
https://doi.org/10.1109/tnano.2003.820779
https://doi.org/10.1109/tnano.2003.820779
Publikováno v:
IEEE Transactions on Nanotechnology. 1:170-175
The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2ae0e9dc118a487dc97b375b78392b99
https://doi.org/10.1109/tnano.2002.807382
https://doi.org/10.1109/tnano.2002.807382
Autor:
Cheon An Lee, Jong Duk Lee, Suk-Kang Sung, Dae Hwan Kim, Kyung-Hoon Chung, Woo Young Choi, Byung-Gook Park
Publikováno v:
Japanese Journal of Applied Physics. 41:4410-4414
A patterning technique to define nanoscale multiple lines is developed and optimized using sidewall structure. About 50 nm poly-Si multiple lines, which have 70 nm as one of the narrowest space, are defined by sidewall multi-line patterning technique
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e8ee029f1f310473ed6669d2421a292
https://doi.org/10.1143/jjap.41.4410
https://doi.org/10.1143/jjap.41.4410
Autor:
Kyung Rok Kim, Doyeol Ahn, Sungwoo Hwang, Suk Kang Sung, Dae Hwan Kim, Bum Ho Choi, Byung-Gook Park, Jong Duk Lee
Publikováno v:
Japanese Journal of Applied Physics. 41:2574-2577
Novel single-electron transistors with sidewall depletion gates on a silicon-on-insulator nano-wire have been fabricated by the conventional very large-scale integration technologies. The fabricated SETs show the controllable characteristics, which c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dfd307317e177599ea08f260ba0f34d
https://doi.org/10.1143/jjap.41.2574
https://doi.org/10.1143/jjap.41.2574
Autor:
Byung-Gook Park, Yong Kyu Lee, Byung Man Kim, Soo Doo Chae, Jae-Sung Sim, Dae Hwan Kim, Suk-Kang Sung, Kyung Rok Kim, Jong Duk Lee
Publikováno v:
Japanese Journal of Applied Physics. 41:2606-2610
The room temperature-operation of a single-electron metal-oxide-semiconductor (MOS) memory with a defined quantum dot fabricated by sidewall patterning technique based on conventional VLSI technologies has been demonstrated without the aid of electro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83f653f592579973b43b2de31aaefe88
https://doi.org/10.1143/jjap.41.2606
https://doi.org/10.1143/jjap.41.2606