Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Sujatha Gowder"'
Autor:
Wenyan Jia, Fulvio Spagna, Rui Song, Dave Bradley, Lily Li, Amanda Tran, Shenggao Li, Michelle Wigton, Xiaoqing Wang, Luke Tong, Deepar Govindrajan, Meng-hung Chen, Chen Ji, Lee Eric M, Sujatha Gowder, Marcus Pasquarella, Matt Duwe, Frank Verdico, Sita Iyer, Michael De Vita, Roan M. Nicholson
Publikováno v:
A-SSCC
This paper presents a 2.5-16 Gbps Gen4 PCIe transceiver with 3-tap Tx EQ, and 8-tap Rx DFE in a 10nm FinFET CMOS technology. A low latency digital CDR is designed supporting a flexible timing recovery scheme. The CDR uses a 3-stage ring DCO, with a l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acafbcd450c1e5c17b902479592f09e0
https://doi.org/10.1109/asscc.2018.8579314
https://doi.org/10.1109/asscc.2018.8579314
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
Autor:
Amanda Tran, Renuka Krishnamurthy, Luke Tong, Jeff Ou, Sitaraman V. Iyer, Xuguang Zhang, Kavitha Prasad, Sujatha Gowder, Doug Gambetta, Hendra Rustam, Yongping Fan, Mamatha Deshpande, John K. Wu, Ravindran Mohanavelu, Chien-chun Lin, Peter Kwok, Fulvio Spagna, Lidong Chen, Roan M. Nicholson, Marcus Pasquarella, Rohit Kumar
Publikováno v:
ISSCC
The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27154442da95010c83fb3f39bacd8a4e
https://doi.org/10.1109/isscc.2010.5433823
https://doi.org/10.1109/isscc.2010.5433823