Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Sujan Pandey"'
Autor:
Binita Pradhan, Urbi Ghimire, Nibedita Chapagain, Nishob Adhikari, Sujan Pandey, Sailesh Pradhan
Publikováno v:
Journal of Nepal Medical Association, Vol 61, Iss 260 (2023)
Introduction: Sepsis is a life-threatening organ dysfunction caused by a dysregulated host response to infection. Serum lactate is useful in predicting the prognosis of critically ill patients. Elevated blood lactate levels as well as delayed clearan
Externí odkaz:
https://doaj.org/article/30233842b41c4fe791f3d596d1104da2
Autor:
Binita Pradhan, Sujan Pandey, Aliska Niroula, Nishob Adhikari, Nibedita Chapagain, Sailesh Pradhan
Publikováno v:
Journal of Nepal Medical Association, Vol 61, Iss 257 (2023)
Introduction: Acute organophosphorus pesticide poisoning is widespread and the most common in many developing countries, including Nepal. Through the inhibition of acetylcholinesterase, organophosphorus poisoning is characterised by the clinical pict
Externí odkaz:
https://doaj.org/article/055be8192b574e31b6a563fa53a1f697
Publikováno v:
Journal of Kathmandu Medical College. :227-231
Background: Metabolic syndrome, a cluster of metabolic abnormalities which bears increased risk for cardiovascular diseases and diabetes mellitus, requires early screening, diagnosis, and timely intervention. Prevalence varies with age, gender, degre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::785e4aa6b3da0978f1f336f5c2a9fbfd
https://doi.org/10.3126/jkmc.v11i4.53664
https://doi.org/10.3126/jkmc.v11i4.53664
Autor:
Klaas Brink, Sujan Pandey
Publikováno v:
IOLTS
This paper is about a single event upset resilient logic design optimization technique for sub-100nm technology nodes. The proposed technique can be used for both combinational as well as sequential circuits. In order to make a logic circuit robust f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9166882f3f1d58b67e3b7e7240eac210
https://doi.org/10.1109/iolts.2012.6313835
https://doi.org/10.1109/iolts.2012.6313835
Publikováno v:
ISCAS
Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scali
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fe78882fbe963b9c61132479895978e
https://doi.org/10.1109/iscas.2008.4542086
https://doi.org/10.1109/iscas.2008.4542086
Publikováno v:
VLSI-SoC
The advancement in process technology has made it possible to integrate multiple processing modules on a single chip. As a result of this, there is a sharp increase of communication traffic on the communication bus architecture. In this case, the tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::786c3fade0d05ac1d601e23f45625e35
https://doi.org/10.1109/vlsisoc.2007.4402518
https://doi.org/10.1109/vlsisoc.2007.4402518
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540744412
PATMOS
PATMOS
In this work, the necessity of combining signal encoding schemes with low-level anti-crosstalk techniques like spacing and shielding is analyzed. It is shown that in order to increase the throughput improvement and/or reduce the power consumption, co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0bffd233feb1dea3621092a02e45526
https://doi.org/10.1007/978-3-540-74442-9_24
https://doi.org/10.1007/978-3-540-74442-9_24
Publikováno v:
International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..
After the partitioning in Hw/Sw co-design, an efficient mapping of hardware components to the target architectures fulfilling both power and delay requirements are still a challenging task for a system designer. In this paper, high level power/delay
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85ec08170911ac908db37e3f136ab534
https://doi.org/10.1109/isscs.2005.1511300
https://doi.org/10.1109/isscs.2005.1511300
Publikováno v:
VLSI-SoC
Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3819236305d9b357bee0dbef5d5b1e70
https://doi.org/10.1109/vlsisoc.2006.313250
https://doi.org/10.1109/vlsisoc.2006.313250
Publikováno v:
VLSI-SoC
Due to shrinking process geometries and an increasing number of chip components in very deep sub-micron technologies, interconnects emerged as a main limiting factor for performance, die area, and power consumption. Buffer allocation, interconnect co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac100ffc5364dc88ac1daa8d256478a0
https://doi.org/10.1109/vlsisoc.2006.313251
https://doi.org/10.1109/vlsisoc.2006.313251