Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Sujal Vora"'
Autor:
M. Arafa, Bob Valentine, Sujal Vora, Sailesh Kottapalli, Ian M. Steiner, Andy Rudoff, Sreenivas Mandava, Akhilesh Kumar, Geetha Vedaraman, Bahaa Fahim, Lily Pao Looi
Publikováno v:
IEEE Micro. 39:29-36
This paper introduces advances in the performance of AI and deep learning inference application on the next generation Intel Xeon Scalable processor, code-named Cascade Lake, which also includes support for Intel Optane DC persistent memory, a breakt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15d126691e872de6d9c0386acfda2a5a
https://doi.org/10.1109/mm.2019.2899330
https://doi.org/10.1109/mm.2019.2899330
Autor:
Edward Wang, Tom Wang, Rizwan Qureshi, Harry Muljono, Hubert Hsieh, Sitaraman V. Iyer, Wei Chen, Min Huang, Kalapi Roy-Neogi, Nagmohan Satti, Sujal Vora, Simon M. Tam
Publikováno v:
ISSCC
SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server processor fabricated on the Intel® 14nm tri-gate CMOS technology with 11-metal layers [1,2]. The SKX processor family has three core-count configurations. Each SK
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2740c08f1e95d83f37c28cd261c6105
https://doi.org/10.1109/isscc.2018.8310170
https://doi.org/10.1109/isscc.2018.8310170
Autor:
Edward Wang, Aaron K. Martin, Simon M. Tam, Shenggao Li, Wei Chen, Raj Varada, Sujal Vora, Harry Muljono, David J. Ayers, Stefan Rusu
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:35-48
This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::142d351fb5c3132be61c729b8745c0e1
https://doi.org/10.1109/jssc.2014.2368933
https://doi.org/10.1109/jssc.2014.2368933
Autor:
Sailesh Kottapalli, Sujal Vora, Stefan Rusu, Matt Ratta, Raj Varada, Harry Muljono, J. Stinson, J. Chang, Simon M. Tam, David J. Ayers
Publikováno v:
ISSCC
This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::131466a8ef50023a6828f6c914c22b7c
https://doi.org/10.1109/jssc.2009.2034076
https://doi.org/10.1109/jssc.2009.2034076
Autor:
B. Cherkauer, Rahul Limaye, J. Chang, Harry Muljono, J. Stinson, Sujal Vora, John Benoit, Simon M. Tam, Justin Leung, Raj Varada, David J. Ayers, Stefan Rusu
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:17-25
This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache impl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf6da9b15f91d02d993e50fc22252f72
https://doi.org/10.1109/jssc.2006.885041
https://doi.org/10.1109/jssc.2006.885041
Autor:
Stefan Rusu, Shenggao Li, Wei Chen, Harry Muljono, Simon M. Tam, Edward Wang, Sujal Vora, Aaron K. Martin, Raj Varada, David J. Ayers
Publikováno v:
ISSCC
The next-generation enterprise Xeon® server processor has 15 dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe42a686fc5a0106c946c76d4813efce
https://doi.org/10.1109/isscc.2014.6757356
https://doi.org/10.1109/isscc.2014.6757356
Autor:
Stefan Rusu, Simon M. Tam, J. Chang, Harry Muljono, Sujal Vora, Raj Varada, David J. Ayers, Matt Ratta
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference.
A 2.3B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24MB shared L3 cache was implemented in a 45nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fe92bb4b10883c5fc10ee19093beeb7
https://doi.org/10.1109/asscc.2009.5357230
https://doi.org/10.1109/asscc.2009.5357230
Autor:
Stefan Rusu, J. Stinson, Sailesh Kottapalli, David J. Ayers, Matt Ratta, Simon M. Tam, Raj Varada, Sujal Vora, J. Chang, Harry Muljono
Publikováno v:
ESSCIRC
This paper presents the power reduction and management techniques for the 45nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leaka
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ec3671abd2362cfa846aed02e206c3b
https://doi.org/10.1109/esscirc.2009.5326028
https://doi.org/10.1109/esscirc.2009.5326028
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
This paper describes a 95 W dual-core 64-bit Xeonreg MP processor implemented in a 65 nm 8 metal layer process. Each processor core has a unified 1MB L2 cache and supports the Intelreg Extended Memory 64 Technology and the Hyper-Threading Technology.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b933bc452d04a4798fd52a8bf4a14c8
https://doi.org/10.1109/asscc.2006.357840
https://doi.org/10.1109/asscc.2006.357840
Publikováno v:
ISSCC
The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2043a109e00da62e90b6762fc59e9a11
https://doi.org/10.1109/isscc.2006.1696202
https://doi.org/10.1109/isscc.2006.1696202