Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Suheng Chen"'
Autor:
Suheng Chen, Benjamin J. Blalock
Publikováno v:
IEICE Electronics Express. 3:529-533
A switched capacitor bandgap voltage reference circuit capable of sub-1-V operation is presented. The proposed circuit generates a sub-1-V reference voltage with a switched capacitor operation, offering several performance advantages over the current
Autor:
N. Nambiar, Benjamin J. Blalock, M.N. Ericson, M. Hale, Charles L. Britton, Chandradevi Ulaganathan, A. Antonacci, Suheng Chen
Publikováno v:
2008 51st Midwest Symposium on Circuits and Systems.
A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage ran
Autor:
Richard W. Berger, Suheng Chen, R. Broughton, Benjamin J. Blalock, K. Cornett, N. Nambiar, Robert Greenwell, Charles L. Britton, Homer Alan Mantooth, B. Prothro, John D. Cressler, Chandradevi Ulaganathan, H. Hoang, Guoyuan Fu, M.N. Ericson
Publikováno v:
2008 51st Midwest Symposium on Circuits and Systems.
A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, ana
Autor:
Bongim Jun, Omeed Momeni, X. Yu, M. Mojarradi, Suheng Chen, Y. Yao, Paul W. Marshall, Benjamin J. Blalock, Chandradevi Ulaganathan, Tuan A. Vo, John D. Cressler, Laleh Najafizadeh, Akil K. Sutton, Cheryl J. Marshall, Fa Dai
Publikováno v:
2007 9th European Conference on Radiation and Its Effects on Components and Systems.
The effects of proton irradiation on the performance of key devices and mixed-signal circuits fabricated in a SiGe BiCMOS IC design platform and intended for emerging lunar missions are presented. High-voltage (HV) transistors, SiGe bandgap reference
A High-Slew Rate SiGe BiCMOS Operational Amplifier for Operation Down to Deep Cryogenic Temperatures
Autor:
Suheng Chen, R. Krithivasan, Chandradevi Ulaganathan, Benjamin J. Blalock, Yuan Lu, Laleh Najafizadeh, Chendong Zhu, John D. Cressler
Publikováno v:
2006 Bipolar/BiCMOS Circuits and Technology Meeting.
We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic
Autor:
Guofu Niu, R. Krithivasan, Suheng Chen, Laleh Najafizadeh, Chendong Zhu, Chandradevi Ulaganathan, John D. Cressler, Alvin J. Joseph, Benjamin J. Blalock, Yan Cui
Publikováno v:
2006 Bipolar/BiCMOS Circuits and Technology Meeting.
We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimi
Publikováno v:
ACM Great Lakes Symposium on VLSI
An improved biasing scheme for NMOS cascode structures for linear voltage regulators is proposed for mixed-signal communication systems. The proposed regulator achieves approximately 40 dB power supply rejection over wide frequency range, 15 mA load
Autor:
Suheng Chen, Paulo Gentil, Ronald D. Schrimpf, Benjamin J. Blalock, J. Vandersand, Charles L. Britton, M.M. Mojarradi, B. Prothro, Sorin Cristoloveanu, K. Akarvardar
Publikováno v:
Présentée, 2006 IEEE Int. SOI Conf.
Présentée, 2006 IEEE Int. SOI Conf., 2006, Grenoble, France. pp.XX
Présentée, 2006 IEEE Int. SOI Conf., 2006, Grenoble, France. pp.XX
A novel voltage-controlled negative differential resistance device, using complementary SOI Four-Gate Transistors (G4-FETs) is presented. Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ba1d8f979231f8f9117e7ba9feca1867
https://hal.archives-ouvertes.fr/hal-00146909
https://hal.archives-ouvertes.fr/hal-00146909
Autor:
M.M. Mojarradi, K. Akarvardar, Suheng Chen, Benjamin J. Blalock, Sorin Cristoloveanu, J. Vandersand
Publikováno v:
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
A new approach for high-voltage analog applications that utilizes SOI four-gate transistors (G/sup 4/-FETs) is presented. The proposed solution achieves high-voltage operation (10 V and higher) with no additional cost of fabrication (compatible with
Autor:
K. Akarvardar, Suheng Chen, M.M. Mojarradi, Sorin Cristoloveanu, Benjamin J. Blalock, P. Gentil
Publikováno v:
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
A novel analog multiplier using SOI four-gate transistors (G/sup 4/-FETs) is presented. Thanks to the multiple inputs of the G/sup 4/-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, com