Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Suguru Tachibana"'
Autor:
Y. Nakagome, Toshiaki Yamanaka, Katsuro Sasaki, K. Takasugi, Hisayuki Higuchi, Suguru Tachibana
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:487-490
The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM usin
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 74:78-89
The following results have been obtained by evaluating the circuit delay times of submicron BiCMOS, CMOS, and ECL gates by the same criterion: (1) analytical relationships to represent the delay time of each circuit by device parameters have been dev
Autor:
Koichiro Ishibashi, K. Norisue, T. Nakazawa, Kunio Uchiyama, Ikuya Kawasaki, Suguru Tachibana, I. Kudoh, Shigezumi Matsui, R. Izawa, Junichi Nishimoto, Yasuhisa Shimazaki, Susumu Narita, K. Hirose, M. Yamamoto, Shinichi Yoshioka
Publikováno v:
Digest of Technical Papers., Symposium on VLSI Circuits..
A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-
Publikováno v:
Digest of Technical Papers., Symposium on VLSI Circuits..
Virtual memory is used in most high-performance computer systems to extend the address space. Virtual addresses are translated by the system into physical addresses at run-time. The translation is usually accelerated by special hardware called a tran
Autor:
Suguru Tachibana, Hisayuki Higuchi, Toshiaki Yamanaka, Y. Nakagome, K. Takasugi, Katsuro Sasaki
Publikováno v:
Proceedings of 1994 IEEE Symposium on VLSI Circuits.
Autor:
Takashi Nishida, Suzuki Makoto, Katsuhiro Shimohigashi, Suguru Tachibana, A. Watanabe, S. Shukuri, T. Hayashi, Takahiro Nagano, Hisayuki Higuchi
Publikováno v:
Digest of Technical Papers., 1990 Symposium on VLSI Circuits.
The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature
Autor:
Takahiro Nagano, S. Shukuri, Suzuki Makoto, A. Watanabe, Hisayuki Higuchi, Katsuhiro Shimohigashi, Suguru Tachibana
Publikováno v:
IEEE Journal of Solid-State Circuits. 24:1233-1237
A 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power
Autor:
Suguru Tachibana, Hisayuki Higuchi, Masanori Odaka, Atsuo Watanabe, Takahide Ikeda, Suzuki Makoto
Publikováno v:
Extended Abstracts of the 1986 International Conference on Solid State Devices and Materials.
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.