Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Sudesna Dash"'
Autor:
Sebastian Turullols, Ha Pham, Yifan YangGong, Yuanjung David Lin, Hoyeol Cho, Heechoul Park, Dawei Huang, Sudesna Dash, Curtis McAllister, Hongping Penny Li, Changku Hwang, Ali Vahidsafa, Chaoyang Zheng, Vijay Srinivasan, Jeffrey S. Brooks, Francis Schumacher, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Alan P. Smith, Paul N. Loewenstein, Robert P. Masleid, Robert T. Golla
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:79-91
The SPARC M7 processor offers up to 3 $\times$ the throughput performance of Oracle's previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a606e12b1bb30f7903054601615aeadb
https://doi.org/10.1109/jssc.2015.2456902
https://doi.org/10.1109/jssc.2015.2456902
Autor:
A. Smith, Curtis McAllister, Youngmoon Choi, M. Elgebaly, Jinuk Luke Shin, Hongping Li, Sebastian Turullols, Georgios Konstadinidis, Robert P. Masleid, Song Kim, M. J. Doherty, Gregory F. Grohoski, H. Sathianathan, Robert T. Golla, Heechoul Park, Sudesna Dash, M. Joshi
Publikováno v:
ISSCC
The SPARC T4 processor introduces the next generation multi-threaded 64b core to deliver up to 5x integer and 7x floating-point single-thread performance improvement over its predecessor. The chip integrates eight cores, an 8-Bank 4 MB L3 Cache, a 76
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7211f5b6f79e8c39c1bce7e99f625b48
https://doi.org/10.1109/jssc.2012.2223036
https://doi.org/10.1109/jssc.2012.2223036
Autor:
Changku Hwang, Paul N. Loewenstein, Penny Li, Hoyeol Cho, Heechoul Park, Sudesna Dash, Francis Schumacher, Jinuk Luke Shin, Yuanjung David Lin, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Robert P. Masleid, Chaoyang Zheng, Curtis McAllister, Vijay Srinivasan, Dawei Huang
Publikováno v:
ISSCC
The SPARC M7 processor delivers more than 3x throughput performance improvement over its predecessor SPARC M6 for commercial applications. It introduces new design features, such as the S4 core, a 64MB L3 cache subsystem with application data integri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::505a30dca4209b053f118f6ef3ee62f4
https://doi.org/10.1109/isscc.2015.7062931
https://doi.org/10.1109/isscc.2015.7062931
Autor:
Sudesna Dash, Curtis McAllister, Greg F. Grohoski, Mary Jo Doherty, Jinuk Luke Shin, Robert T. Golla, Hongping Li
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
The SPARC T4 processor introduces the next generation multi-threaded S3 core and delivers a significant single-thread performance improvement over its predecessor. The chip integrates eight S3 cores, an 8-Bank 4MB L3 Cache, a 768GB/sec crossbar, a me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::813ee906963ca0dc03a6c3eac24fef7a
https://doi.org/10.1109/ipec.2012.6522613
https://doi.org/10.1109/ipec.2012.6522613
Autor:
Jinuk Luke Shin, Heechoul Park, Hongping Li, Alan Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Robert Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister
Publikováno v:
2012 IEEE International Solid-State Circuits Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::024dd69bd2b9997947e35e430d855769
https://doi.org/10.1109/isscc.2012.6176878
https://doi.org/10.1109/isscc.2012.6176878