Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Subrat Mishra"'
Autor:
Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Pieter Weckx, Francky Catthoor
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:1668-1676
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7734d002650ddb2741c52a55c7b99b8f
https://doi.org/10.1109/tvlsi.2022.3207553
https://doi.org/10.1109/tvlsi.2022.3207553
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:1757-1769
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::934c562e5577bf54ff62683320921210
https://doi.org/10.1109/tvlsi.2022.3177861
https://doi.org/10.1109/tvlsi.2022.3177861
Autor:
Subrat Mishra, A. Thirunavukkarasu, Chetan Kumar Dabhi, Nilesh Goel, Hussam Amrouch, Souvik Mahapatra, Yogesh Singh Chauhan, Narendra Parihar, Jorg Henkel, Jerin Joe
Publikováno v:
IEEE Transactions on Electron Devices. 66:316-323
A framework is proposed for activity-dependent timing degradation due to p-FET negative bias temperature instability (NBTI) in digital circuits. A fixed-time compact model is proposed for NBTI and validated with physical model predictions for various
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f7defda268c54e9f54bf9875bdfda6e6
https://doi.org/10.1109/ted.2018.2882229
https://doi.org/10.1109/ted.2018.2882229
Autor:
Jorg Henkel, Souvik Mahapatra, Hussam Amrouch, Karansingh Thakor, Chetan Kumar Dabhi, Subrat Mishra, Jerin Joe, Yogesh Singh Chauhan
Publikováno v:
IEEE Transactions on Electron Devices. 66:271-278
A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::089066752cf2e0a2120d2361ac9061bc
https://doi.org/10.1109/ted.2018.2875813
https://doi.org/10.1109/ted.2018.2875813
Publikováno v:
2021 IEEE International Reliability Physics Symposium (IRPS)
IRPS
IRPS
Design margins are necessary to ensure reliable operation of integrated circuits over extreme ranges of environmental variations (Voltage, Temperature) and manufacturing Process variations. On top of these PVT variations, aging related parametric dri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::49b0a8f94b7bcf96854c0e9239f132e8
Publikováno v:
2020 21st National Power Systems Conference (NPSC).
The recent advancement has seen a lot of changes in Technology. Technology, like the Internet of Things, has been serving Purpose like integrating things and working effectively to serve humanity. The Smart campus is the IoT based approach to connect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5092175fda5b943b02ea75970f1b27d4
https://doi.org/10.1109/npsc49263.2020.9331898
https://doi.org/10.1109/npsc49263.2020.9331898
Publikováno v:
2020 IEEE International Reliability Physics Symposium (IRPS)
IRPS
IRPS
A common approach to incorporate workload dependent aging in circuits is to use an effective stress time or so-called signal probability (SP) to calculate degradation under realistic workload scenarios. However, this approach is not fully physics-bas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::48a72c4d445bcf39b690a365fb9d36f8
Autor:
Subrat Mishra, Yogesh Singh Chauhan, Narendra Parihar, Chetan Kumar Dabhi, Souvik Mahapatra, R Anandkrishnan
Publikováno v:
IEEE Transactions on Electron Devices. 65:4846-4853
A Monte Carlo SPICE framework is proposed to evaluate the impact of negative bias temperature instability (NBTI) variability on performance and static power ( ${P}_{\text {S}}$ ) of static random access memory (SRAM) array on 14-nm node FinFETs. Gamm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5aa31d7eba02dc8570aa6b347c73af19
https://doi.org/10.1109/ted.2018.2869669
https://doi.org/10.1109/ted.2018.2869669
Autor:
Hiu Yung Wong, Souvik Mahapatra, Subrat Mishra, Ravi Tiwari, Rakesh P Rao, Ankush Chaudhary, Victor Moroz
Publikováno v:
IEEE Transactions on Electron Devices. 63:4624-4631
The kinetics of trap generation during negative-bias temperature instability (NBTI) stress in pMOSFETs, as governed by the double interface H–H2 reaction–diffusion (RD) model, is incorporated for the first time in a commercial technology computer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87000522fe96e0bf33124904784154d0
https://doi.org/10.1109/ted.2016.2615163
https://doi.org/10.1109/ted.2016.2615163
Publikováno v:
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Negative-Bias Temperature Instability (NBTI) degrades the drive current of p-channel FinFET because defect centers are depassivated as hydrogen diffuses away under negative bias and elevated temperature. We propose incorporating hydrogen in the gate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15616c31a767b817694375aad19da5cc
https://doi.org/10.23919/sispad.2017.8085274
https://doi.org/10.23919/sispad.2017.8085274