Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Subhas Bothra"'
Publikováno v:
EDFA Technical Articles. 1:19-30
Passive voltage contrast (PVC) has traditionally been used by semiconductor engineers for end-of-line post-mortem analysis. PVC distinguishes between open and short structures and is both nondestructive and noncontact. When applied during process dev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0636715332733dec5e3c023f3e9bebde
https://doi.org/10.31399/asm.edfa.1999-3.p019
https://doi.org/10.31399/asm.edfa.1999-3.p019
Publikováno v:
Journal of The Electrochemical Society. 142:L208-L211
Gate oxide damage resulting from high density plasma chemical vapor deposition of silicon oxide was investigated using damage sensitive antenna structures with area ratios up to 200,000 :1. Significant damage was detected from an unoptimized oxide de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bea0b60cb46b3dbfbd6ddeb185c0f32c
https://doi.org/10.1149/1.2048449
https://doi.org/10.1149/1.2048449
Autor:
Malcolm MacIntosh, Ed Chien, Dandan Li, C.P. Lee, Vikram Magoon, Yuyu Chang, Shahla Khorram, Bojko Marholev, Kevin Chien, Stephen Au, Zhenhua Liu, Amir Hadji-Abdolhamid, Paul Chang, Jesse Castaneda, Jacob Rael, Vinay Chandrasekhar, Keith Carter, Ali Afsahi, Edwin X. Li, Mark Gonikberg, Maryam Rofougaran, Ali Sarfaraz, Reza Rofougaran, Kimmer Kim, Yury Gonikberg, Tom Li, Siukai Mak, S. Bouras, Dayo Ojo, Seema B. Anand, Luis Gutierrez, Lijun Zhang, Bobby Lee, Madjid Hafizi, Carol Barrett, M. Nariman, Alireza Zolfaghari, Kishore Rama Rao, Marcellus Forbes, Arya Behzad, Brima Ibrahim, Zhimin Zhao, Subhas Bothra, Steve Wu, Rozi Roufoogaran, Iqbal Bhatti, Colin Fraser, Hooman Darabi, Prasad Seetharam
Publikováno v:
ISSCC
The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f2320dc5d8a3e7c33269e30c34b128f2
https://doi.org/10.1109/isscc.2010.5433962
https://doi.org/10.1109/isscc.2010.5433962
Publikováno v:
1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).
An investigation into CMOS gate oxide failures during the process development of an advanced 0.25/spl mu/m CMOS ASIC process is presented. Using a SEM technique called passive voltage contrast (PVC), specific backend process steps contributing to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec8b5db72b8a4322891cbee5416c3f3b
https://doi.org/10.1109/ppid.1998.725596
https://doi.org/10.1109/ppid.1998.725596
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
The charge based capacitance measurement (CBCM) technique (Chen et al, IEDM p. 69, 1996) was used in order to measure femto-farad level intermetal capacitances between metal lines in different configurations. The results are presented and compared wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa066fd599d8f1c677ab86a03fcf758d
https://doi.org/10.1109/iitc.1998.704785
https://doi.org/10.1109/iitc.1998.704785
Publikováno v:
1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).
Accelerated corrosion of tungsten in tungsten-plug vias was observed due to charging of certain test structures during metal etch in a plasma etcher. This charge is shown to be a positive charge and is responsible for the accelerated dissolution of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8cf3daeae087aaabaf333c845ae982f
https://doi.org/10.1109/ppid.1998.725615
https://doi.org/10.1109/ppid.1998.725615
Publikováno v:
International Symposium for Testing and Failure Analysis.
An investigation into a high resistance via problem during the development phase of an advanced 0.25µm CMOS ASIC process is presented. The electrical signature of the via problem was low yield on fully processed device wafers. Further testing reveal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e83315c0f328142a8240960772dfe9a4
https://doi.org/10.31399/asm.cp.istfa1998p0273
https://doi.org/10.31399/asm.cp.istfa1998p0273
Autor:
Subhas Bothra, Samit Sengupta
Publikováno v:
SPIE Proceedings.
Tight interconnect design rules associated with 0.25 micrometer technology and below introduces a number of challenges in backend integration in the course of developing an appropriate process architecture. In this paper, the effect of the underlying
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e00f0f3f203163bc3a8c67aecdc06633
https://doi.org/10.1117/12.324042
https://doi.org/10.1117/12.324042
Publikováno v:
MRS Proceedings. 514
Advanced interconnect fabrication may require alternative TiITiN processes, such as an ionized metal plasma (IMP) sputtering technique to deposit Ti/TiN liner for sufficient step coverage in high aspect ratio contacts/vias. Since TiN is also widely u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4eb15a82ef723a5421cd76382ef5bcef
https://doi.org/10.1557/proc-514-539
https://doi.org/10.1557/proc-514-539
Publikováno v:
International Symposium for Testing and Failure Analysis.
Optimization of the passivation scheme for a 0.35 μm TLM process is presented. The passivation layer is required to provide mechanical and chemical protection during the assembly and packaging process and long term environmental protection. The pass
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12d8438793e1097f72f317ce571653aa
https://doi.org/10.31399/asm.cp.istfa1997p0293
https://doi.org/10.31399/asm.cp.istfa1997p0293