Zobrazeno 1 - 10
of 45
pro vyhledávání: '"Su-Ching Chung"'
Publikováno v:
Frontiers in Psychology, Vol 15 (2024)
IntroductionEmployee assistance programs require resources and manpower of various natures across different types of public sector organization.MethodsThis study began by outlining elements for comparing employee assistance programs’ evaluation cri
Externí odkaz:
https://doaj.org/article/746fa38b4a52470cacf8ec2a2336b9d4
Autor:
Ho, Ying-Ning, Chiang, Hsing-Mei, Chao, Chih-Ping, Su, Ching-Chung, Hsu, Hui-Fang, Guo, Chen-tong, Hsieh, Ju-Liang, Huang, Chieh-Chen
Publikováno v:
Plant and Soil, 2015 Feb 01. 387(1/2), 295-306.
Externí odkaz:
https://www.jstor.org/stable/24371238
Publikováno v:
2018 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC).
Three dimensional integrated circuit technology has been recently received much interests because it could meet the requirements such as small form factor, high performance, low cost and heterogeneous integration in system-in-package technologies for
Autor:
Yu-Min Lin, Chia-Wen Fan, Chau-Jie Zhan, Wen-Wei Shen, Huan-Chun Fu, Su-Ching Chung, Su-Mei Chen, Chia-Wen Chiang, Jen-Chun Wang, Wei-Chung Lo, Hsiang-Hung Chang, Yuan-Chang Lee, Ching-Kuan Lee, Yung Jean Lu
Publikováno v:
2016 International Conference on Electronics Packaging (ICEP).
In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside
Autor:
Kuo-Chyuan Chen, Tao-Chih Chang, Ren-Shin Cheng, Su-Ching Chung, Su-Yu Fun, Chia-Wen Fan, Chau-Jie Zhan, Yu-Lan Lu
Publikováno v:
2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Flip chip package has been reported to be an ideal package solution of high bandwidth devices because of a lower power loss and a short transmission route of signal. However, some failure modes such as solder joint crack, delamination of substrate or
Autor:
Su-Mei Chen, Yu-Min Lin, Huan-Chun Fu, Yung Jean Lu, Chia-Wen Fan, Jen-Chun Wang, C. W. Chiang, Wei-Chung Lo, Yuan-Chang Lee, Ching-Kuan Lee, Chau-Jie Zhan, Wen-Wei Shen, Su-Ching Chung
Publikováno v:
2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabric
Autor:
Chau-Jie Zhan, Yu-Min Lin, Ren-Shin Cheng, Jing-Ye Juang, Chia-Wen Fan, Su-Yu Fun, Tao-Chih Chang, Su-Ching Chung, Shi-Yi Huang, Yu-Wei Huang
Publikováno v:
2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-s
Publikováno v:
2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).
The wide-band-gap power devices such as SiC and GaN semiconductors have excellent physic properties, such as high breakdown voltage, high power density, high switching frequency and very low power loss under high temperature, and are believed to be t
Autor:
Ren-Shin Cheng, Chau-Jie Zhan, Su-Yu Fun, Su-Ching Chung, Kuo-Chyuan Chen, Yu-Lan Lu, Chia-Wen Fan, Tao-Chih Chang
Publikováno v:
2015 10th International Microsystems, Packaging, Assembly & Circuits Technology Conference (IMPACT); 2015, p241-244, 4p
Autor:
John H. Lau, Su-Mei Chen, Yu-Wei Huang, Jon-Shiou Peng, Yu-Lan Lu, Pai-Cheng Chang, Chia-Wen Fan, Shin-Yi Huang, Chau-Jie Zhan, Mei-Lun Wu, Yu-Min Lin, Jing-Ye Juang, Su-Ching Chung
Publikováno v:
2013 IEEE 63rd Electronic Components and Technology Conference.
Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip s